Patents by Inventor Hidekazu Noguchi

Hidekazu Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9076503
    Abstract: A word driver drives a word line with a first power supply voltage and with a second power supply voltage which has a potential lower than the first power potential, respectively in a first time period and in a second time period following the first time period for activating the word line.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 7, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hidekazu Noguchi
  • Patent number: 9053759
    Abstract: The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: June 9, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hidekazu Noguchi
  • Patent number: 8726106
    Abstract: Disclosed herein is a semiconductor device that includes selection lines selected based on an access address, a first hit signal generation circuit activating a first hit signal when the access address is coincident with a programmed address that designates a defective selection line included in the selection lines, and a first redundant selection line selected when the first hit signal is activated. The first hit signal generation circuit deactivates the first hit signal when a value of the access address is in a first address range even if the access address is coincident with the programmed address.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: May 13, 2014
    Inventor: Hidekazu Noguchi
  • Publication number: 20130135947
    Abstract: The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 30, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Hidekazu Noguchi
  • Publication number: 20130007510
    Abstract: Disclosed herein is a semiconductor device that includes selection lines selected based on an access address, a first hit signal generation circuit activating a first hit signal when the access address is coincident with a programmed address that designates a defective selection line included in the selection lines, and a first redundant selection line selected when the first hit signal is activated. The first hit signal generation circuit deactivates the first hit signal when a value of the access address is in a first address range even if the access address is coincident with the programmed address.
    Type: Application
    Filed: June 26, 2012
    Publication date: January 3, 2013
    Inventor: Hidekazu NOGUCHI
  • Publication number: 20120320699
    Abstract: A word driver drives a word line with a first power supply voltage and with a second power supply voltage which has a potential lower than the first power potential, respectively in a first time period and in a second time period following the first time period for activating the word line.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 20, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Hidekazu NOGUCHI
  • Publication number: 20120307578
    Abstract: Disclosed herein is a semiconductor device that includes a plurality of normal memory cells, a plurality of first normal lines each coupled to corresponding one or ones of the normal memory cells, a plurality of redundant memory cells, and first and second redundant lines each coupled to corresponding one or ones of the redundant memory cells. The first redundant line is configured to replace selected one or ones of the normal lines and the second line is configure to replace any one of the selected one or ones of the normal lines and remaining one or ones of the normal lines.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 6, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Hidekazu NOGUCHI
  • Patent number: 8125248
    Abstract: There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: February 28, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Publication number: 20110057685
    Abstract: There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed.
    Type: Application
    Filed: August 13, 2010
    Publication date: March 10, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Hidekazu Noguchi
  • Patent number: 7295055
    Abstract: A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A clock signal is inverted by an input buffer and applied to a NAND gate together with a mask signal. When the signal from the NAND gate rises, the signal of the second integrating portion falls after a delay time due to the integration circuit. The signal from the NAND gate is applied together with the signal from the second integrating portion to a second NAND gate, and the signal from the second NAND gate is fixed at ā€œLā€ during the period from the time of the rise of the clock signal for the duration of the delay time of the integration circuit. The signal from the second NAND gate is delayed by a third integrating portion and a delay time of the third integrating portion is added by an AND gate to generate a mask signal.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: November 13, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hidekazu Noguchi, Hidenori Uehara
  • Patent number: 7161405
    Abstract: A level shift circuit includes first and second inverters and an inversion circuit. The first inverter has a first input terminal and a first output terminal for generating the output signal. The first inverter includes a first transistor having a first current driving capacity. The second inverter has a second input terminal connected to the first output terminal and a second output terminal connected to the first input terminal. The second inverter includes a second transistor having a second current driving capacity smaller than the first capacity. The inversion circuit has an output terminal connected to the first input terminal. The inversion circuit receives an input signal including a first input signal and a second input signal one of which is a one-shot pulse signal. The inversion circuit includes a third transistor having a third current driving capacity smaller than the first capacity and larger than the second capacity.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: January 9, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Publication number: 20060119716
    Abstract: A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A clock signal is inverted by an input buffer and applied to a NAND gate together with a mask signal. When the signal from the NAND gate rises, the signal of the second integrating portion falls after a delay time due to the integration circuit. The signal from the NAND gate is applied together with the signal from the second integrating portion to a second NAND gate, and the signal from the second NAND gate is fixed at ā€œLā€ during the period from the time of the rise of the clock signal for the duration of the delay time of the integration circuit. The signal from the second NAND gate is delayed by a third integrating portion and a delay time of the third integrating portion is added by an AND gate to generate a mask signal.
    Type: Application
    Filed: September 1, 2005
    Publication date: June 8, 2006
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Hidekazu Noguchi, Hidenori Uehara
  • Patent number: 7005931
    Abstract: An oscillator circuit having an oscillation period moderately varying such that it is short at high temperature but long at low temperature and wherein a maximum value of oscillation period at low temperature can be set. By coupling a resistance parallel circuit having a resistance element having a resistance value decreasing with increasing temperature and a resistance element having a resistance value nondependent upon temperature at between the main electrodes of PMOST and NMOST, the output signal of an inverter is caused to vary with temperature. A ring oscillator circuit outputs an oscillation period short at high temperature but long at low temperature. Meanwhile, because oscillation period is greatly affected by a resistance value of the resistant element not dependent upon temperature at low temperature, a maximum value of oscillation period can be set.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: February 28, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Patent number: 6977851
    Abstract: A semiconductor memory device has a redundant memory cell array having redundant memory cells arranged in redundant rows and columns and has first and second fuse blocks. The first fuse block has first fuses for corresponding to an address of a row address signal. The second fuse block has second fuses for corresponding to a column address signal. The first fuse block stores an address of a defective row of the memory cell and the second fuse block stores an address of a defective column of the memory cell. Furthermore, the semiconductor memory device has an address matching detector connected with the first and second fuses. The address matching detector checks consistency of the address of the row or column address signal with the address of the defective row or column.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: December 20, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Publication number: 20050047225
    Abstract: A semiconductor memory device has a redundant memory cell array having redundant memory cells arranged in redundant rows and columns and has first and second fuse blocks. The first fuse block has first fuses for corresponding to an address of a row address signal. The second fuse block has second fuses for corresponding to a column address signal. The first fuse block stores an address of a defective row of the memory cell and the second fuse block stores an address of a defective column of the memory cell. Furthermore, the semiconductor memory device has an address matching detector connected with the first and second fuses. The address matching detector checks consistency of the address of the row or column address signal with the address of the defective row or column.
    Type: Application
    Filed: June 28, 2004
    Publication date: March 3, 2005
    Applicant: Oki Electric Industry Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Publication number: 20050007175
    Abstract: A level shift circuit includes first and second inverters and an inversion circuit. The first inverter has a first input terminal and a first output terminal for generating the output signal. The first inverter includes a first transistor having a first current driving capacity. The second inverter has a second input terminal connected to the first output terminal and a second output terminal connected to the first input terminal. The second inverter includes a second transistor having a second current driving capacity smaller than the first capacity. The inversion circuit has an output terminal connected to the first input terminal. The inversion circuit receives an input signal including a first input signal and a second input signal one of which is a one-shot pulse signal. The inversion circuit includes a third transistor having a third current driving capacity smaller than the first capacity and larger than the second capacity.
    Type: Application
    Filed: March 31, 2004
    Publication date: January 13, 2005
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Hidekazu Noguchi
  • Publication number: 20040257164
    Abstract: An oscillator circuit having an oscillation period moderately varying such that it is short at high temperature but long at low temperature and wherein a maximum value of oscillation period at low temperature can be set. By coupling a resistance parallel circuit having a resistance element having a resistance value decreasing with increasing temperature and a resistance element having a resistance value nondependent upon temperature at between the main electrodes of PMOST and NMOST, the output signal of an inverter is caused to vary with temperature. A ring oscillator circuit outputs an oscillation period short at high temperature but long at low temperature. Meanwhile, because oscillation period is greatly affected by a resistance value of the resistant element not dependent upon temperature at low temperature, a maximum value of oscillation period can be set.
    Type: Application
    Filed: February 6, 2004
    Publication date: December 23, 2004
    Applicant: Oki Electric Industry Co. Ltd.
    Inventor: Hidekazu Noguchi
  • Patent number: 6751128
    Abstract: The period of time required for a parallel test can be shortened by widening the application range of the parallel test. In the semiconductor memory device having memory cell portions, there are provided a column controller that simultaneously activates a plurality of columns which are subject to degenerate substitution in a column redundant substitution; and a data read-out circuit that simultaneously reads out the data from a plurality of memory cells as selected by the above plurality of columns.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: June 15, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Koji Kuroki, Hidekazu Noguchi
  • Patent number: 6738299
    Abstract: A semiconductor memory device includes a redundancy circuit having predecode signal lines, a fuse predecode circuit, fuse decode circuit and an address decode circuit. The fuse predecode circuit is connected to the fuse predecode signal lines. The fuse predecode circuit includes drivers each of which generates a drive signal in response to one of first address signals received by the fuse predecode circuit. The fuse predecode circuit further includes terminal circuits connected to the predecode signal lines for latching signals appeared thereon, and fuse circuits each of which is connected between one of the predecode signal lines and a first potential source. Each of the fuse circuits includes a transistor having a control terminal connected to one of the drivers and a fuse connected to the transistor in series.
    Type: Grant
    Filed: January 27, 2003
    Date of Patent: May 18, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Publication number: 20030169628
    Abstract: A semiconductor memory device includes a redundancy circuit having predecode signal lines, a fuse predecode circuit, fuse decode circuit and an address decode circuit. The fuse predecode circuit is connected to the fuse predecode signal lines. The fuse predecode circuit includes drivers each of which generates a drive signal in response to one of first address signals received by the fuse predecode circuit. The fuse predecode circuit further includes terminal circuits connected to the predecode signal lines for latching signals appeared thereon, and fuse circuits each of which is connected between one of the predecode signal lines and a first potential source. Each of the fuse circuits includes a transistor having a control terminal connected to one of the drivers and a fuse connected to the transistor in series.
    Type: Application
    Filed: January 27, 2003
    Publication date: September 11, 2003
    Inventor: Hidekazu Noguchi