Patents by Inventor Hidekazu Noguchi

Hidekazu Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10878862
    Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the timing for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yangsung Joo, Hidekazu Noguchi
  • Publication number: 20200211632
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Hidekazu Noguchi
  • Publication number: 20200202921
    Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 25, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Masaru Morohashi, Hidekazu Noguchi
  • Publication number: 20200090713
    Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the timing for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Yangsung Joo, Hidekazu Noguchi
  • Patent number: 10580475
    Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Masaru Morohashi, Hidekazu Noguchi
  • Publication number: 20190228815
    Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Masaru Morohashi, Hidekazu Noguchi
  • Publication number: 20150269988
    Abstract: The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Applicant: PS4 Luxco S.a.r.l.
    Inventor: Hidekazu Noguchi
  • Patent number: 9076503
    Abstract: A word driver drives a word line with a first power supply voltage and with a second power supply voltage which has a potential lower than the first power potential, respectively in a first time period and in a second time period following the first time period for activating the word line.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 7, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hidekazu Noguchi
  • Patent number: 9053759
    Abstract: The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: June 9, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hidekazu Noguchi
  • Patent number: 8726106
    Abstract: Disclosed herein is a semiconductor device that includes selection lines selected based on an access address, a first hit signal generation circuit activating a first hit signal when the access address is coincident with a programmed address that designates a defective selection line included in the selection lines, and a first redundant selection line selected when the first hit signal is activated. The first hit signal generation circuit deactivates the first hit signal when a value of the access address is in a first address range even if the access address is coincident with the programmed address.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: May 13, 2014
    Inventor: Hidekazu Noguchi
  • Publication number: 20130135947
    Abstract: The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group.
    Type: Application
    Filed: November 21, 2012
    Publication date: May 30, 2013
    Applicant: Elpida Memory, Inc.
    Inventor: Hidekazu Noguchi
  • Publication number: 20130007510
    Abstract: Disclosed herein is a semiconductor device that includes selection lines selected based on an access address, a first hit signal generation circuit activating a first hit signal when the access address is coincident with a programmed address that designates a defective selection line included in the selection lines, and a first redundant selection line selected when the first hit signal is activated. The first hit signal generation circuit deactivates the first hit signal when a value of the access address is in a first address range even if the access address is coincident with the programmed address.
    Type: Application
    Filed: June 26, 2012
    Publication date: January 3, 2013
    Inventor: Hidekazu NOGUCHI
  • Publication number: 20120320699
    Abstract: A word driver drives a word line with a first power supply voltage and with a second power supply voltage which has a potential lower than the first power potential, respectively in a first time period and in a second time period following the first time period for activating the word line.
    Type: Application
    Filed: June 11, 2012
    Publication date: December 20, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Hidekazu NOGUCHI
  • Publication number: 20120307578
    Abstract: Disclosed herein is a semiconductor device that includes a plurality of normal memory cells, a plurality of first normal lines each coupled to corresponding one or ones of the normal memory cells, a plurality of redundant memory cells, and first and second redundant lines each coupled to corresponding one or ones of the redundant memory cells. The first redundant line is configured to replace selected one or ones of the normal lines and the second line is configure to replace any one of the selected one or ones of the normal lines and remaining one or ones of the normal lines.
    Type: Application
    Filed: June 4, 2012
    Publication date: December 6, 2012
    Applicant: Elpida Memory, Inc.
    Inventor: Hidekazu NOGUCHI
  • Patent number: 8125248
    Abstract: There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: February 28, 2012
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Publication number: 20110057685
    Abstract: There is provided a semiconductor device including: logic circuit elements disposed within a specific region in respective functional blocks of a logic circuit having a plurality of the functional blocks provided one for each functional unit; and a decoupling capacitor disposed in a region within each of the functional blocks at which no logic circuit element is disposed.
    Type: Application
    Filed: August 13, 2010
    Publication date: March 10, 2011
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Hidekazu Noguchi
  • Patent number: 7295055
    Abstract: A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A clock signal is inverted by an input buffer and applied to a NAND gate together with a mask signal. When the signal from the NAND gate rises, the signal of the second integrating portion falls after a delay time due to the integration circuit. The signal from the NAND gate is applied together with the signal from the second integrating portion to a second NAND gate, and the signal from the second NAND gate is fixed at ā€œLā€ during the period from the time of the rise of the clock signal for the duration of the delay time of the integration circuit. The signal from the second NAND gate is delayed by a third integrating portion and a delay time of the third integrating portion is added by an AND gate to generate a mask signal.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: November 13, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Hidekazu Noguchi, Hidenori Uehara
  • Patent number: 7161405
    Abstract: A level shift circuit includes first and second inverters and an inversion circuit. The first inverter has a first input terminal and a first output terminal for generating the output signal. The first inverter includes a first transistor having a first current driving capacity. The second inverter has a second input terminal connected to the first output terminal and a second output terminal connected to the first input terminal. The second inverter includes a second transistor having a second current driving capacity smaller than the first capacity. The inversion circuit has an output terminal connected to the first input terminal. The inversion circuit receives an input signal including a first input signal and a second input signal one of which is a one-shot pulse signal. The inversion circuit includes a third transistor having a third current driving capacity smaller than the first capacity and larger than the second capacity.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: January 9, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Publication number: 20060119716
    Abstract: A semiconductor integrated circuit includes a integration circuit which has a first integrating portion and a second integrating portion. The semiconductor integrated circuit also includes a data input portion, data processing portion and data output portion. A clock signal is inverted by an input buffer and applied to a NAND gate together with a mask signal. When the signal from the NAND gate rises, the signal of the second integrating portion falls after a delay time due to the integration circuit. The signal from the NAND gate is applied together with the signal from the second integrating portion to a second NAND gate, and the signal from the second NAND gate is fixed at ā€œLā€ during the period from the time of the rise of the clock signal for the duration of the delay time of the integration circuit. The signal from the second NAND gate is delayed by a third integrating portion and a delay time of the third integrating portion is added by an AND gate to generate a mask signal.
    Type: Application
    Filed: September 1, 2005
    Publication date: June 8, 2006
    Applicant: Oki Electric Industry Co., Ltd.
    Inventors: Hidekazu Noguchi, Hidenori Uehara
  • Patent number: 7005931
    Abstract: An oscillator circuit having an oscillation period moderately varying such that it is short at high temperature but long at low temperature and wherein a maximum value of oscillation period at low temperature can be set. By coupling a resistance parallel circuit having a resistance element having a resistance value decreasing with increasing temperature and a resistance element having a resistance value nondependent upon temperature at between the main electrodes of PMOST and NMOST, the output signal of an inverter is caused to vary with temperature. A ring oscillator circuit outputs an oscillation period short at high temperature but long at low temperature. Meanwhile, because oscillation period is greatly affected by a resistance value of the resistant element not dependent upon temperature at low temperature, a maximum value of oscillation period can be set.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: February 28, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidekazu Noguchi