Patents by Inventor Hidekazu Yamamoto

Hidekazu Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6461447
    Abstract: A substrate having a surface on which silicon is epitaxially grown; wherein the substrate is cut from an oxygen induced stacking fault generation area of a single crystal silicon rod grown by the Czochralski method.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: October 8, 2002
    Assignee: Mitsubish Denki Kabushiki Kaisha
    Inventors: Hiroshi Shinyashiki, Hiroshi Koya, Tomonori Yamaoka, Kazuhito Matsukawa, Yasuhiro Kimura, Hidekazu Yamamoto
  • Patent number: 6399460
    Abstract: A method of manufacturing a semiconductor device including the steps of (a) forming an element isolation insulating film in an element isolation region of a SOI substrate of a stacked structure in which a semiconductor substrate, insulating layer, and semiconductor layer are stacked in this order, and (b) forming, in an element formation region of the SOI substrate, a transistor having a channel formation region selectively disposed in a main surface of the semiconductor layer, a gate structure on the channel formation region, and source/drain regions disposed is the main surface of the semiconductor layer and the adjacent channel formation region. The method also includes the step of (c) selectively growing, after said steps (a) and (b), a polycrystal semiconductor layer on the source/drain regions in a self-aligned manner, which is prescribed by the element isolation insulating film and the gate structure.
    Type: Grant
    Filed: October 5, 2000
    Date of Patent: June 4, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Hidekazu Yamamoto
  • Patent number: 6319331
    Abstract: An object is to provide a method for processing a semiconductor substrate that can form an oxide film less prone to take in impurities affecting semiconductor characteristics on the surface. An RCA-cleaned semiconductor substrate is treated with diluted hydrofluoric acid (HF) to remove a native oxide film formed on the semiconductor substrate during the RCA cleaning process (step S8). For conditions of the treatment with diluted hydrofluoric acid, the concentration of hydrofluoric acid is about 50%, the ratio of hydrofluoric acid to pure water is 1:100, and the processing time is about one minute. Finally, the semiconductor substrate from which the native oxide film has been removed is stored in a clean atmosphere of oxygen for a predetermined time period to form an oxide film on the semiconductor substrate surface (step S9). The percentage of oxygen in the atmosphere of oxygen in the place for storage is about 20 to 100%.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: November 20, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Morihiko Kume, Hidekazu Yamamoto
  • Patent number: 6271541
    Abstract: A semiconductor device is provided which is capable of removing the heavy metal impurity in a SOI layer by gettering, and realizing an improvement in breakdown voltage and reliability. The semiconductor device comprises polysilicon regions functioning as a gettering site, which are selectively formed in a buried fashion, such as to make no contact with a gate insulating film and an element isolation insulating film, in a main surface of part of a SOI layer where a drain region and a source region are disposed; and contact holes being filled with polysilicon plug functioning as a gettering site, and extending through an interlayer insulating film between an upper surface of the interlayer insulating film and an upper surface of the polysilicon regions.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: August 7, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuo Yamaguchi, Hidekazu Yamamoto
  • Patent number: 6252294
    Abstract: A semiconductor device and a semiconductor storage device having an SOI structure and being enable sufficient gettering performance without imposing limitations on the freedom of design of an LSI circuit. A semiconductor device includes a semiconductor wafer of SOI structure which has a insulation layer and a silicon layer provided thereon, wherein the semiconductor wafer includes a plurality of element fabrication regions where semiconductor elements are fabricated, and a cutting region provided between the element fabrication regions. Gettering sites are formed in the cutting region by means of embedding a gettering member into grooves of predetermined depth.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: June 26, 2001
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Nobuyoshi Hattori, Hideki Naruoka, Hidekazu Yamamoto
  • Publication number: 20010002704
    Abstract: A semiconductor device is provided which is capable of removing the heavy metal impurity in a SOI layer by gettering, and realizing an improvement in breakdown voltage and reliability. The semiconductor device (50) comprises polysilicon regions (17, 18) functioning as a gettering site, which are selectively formed in a buried fashion, such as to make no contact with a gate insulating film (6) and an element isolation insulating film (11), in a main surface of part of a SOI layer (4) where a drain region (8) and a source region (9) are disposed; and contact holes (13, 15) being filled with polysilicon plug functioning as a gettering site, and extending through an interlayer insulating film (12) between an upper surface of the interlayer insulating film (12) and an upper surface of the polysilicon regions (17, 18).
    Type: Application
    Filed: December 30, 1999
    Publication date: June 7, 2001
    Inventors: YASUO YAMAGUCHI, HIDEKAZU YAMAMOTO
  • Patent number: 5876819
    Abstract: A semiconductor substrate with no reduction in the effective usage area and mechanical strength, and non-uniformity of the resist film thickness, and method of manufacturing and using the same are obtained. A detection mark for detecting the crystal orientation of a silicon wafer having an outer perimeter entirely of a circular contour is formed at a predetermined region of the silicon wafer. The crystal orientation of the semiconductor wafer can easily be detected with the outer perimeter still taking a circular contour. Therefore, various problems encountered in a conventional semiconductor substrate having an orientation flat or notch such as reduction in mechanical strength and effective usage area, and non-uniformity of the resist film can be circumvented.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: March 2, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuhiro Kimura, Keiji Yamauchi, Hidekazu Yamamoto, Shigehisa Yamamoto, Masafumi Katsumata, Yasukazu Mukogawa, Hajime Watanabe
  • Patent number: 5539461
    Abstract: An image sensor includes a photoelectric conversion element, a first MOS transistor having having a gate connected to the photoelectric conversion element, a second MOS transistor connected in series with the first transistor, and a third MOS transistor connected in series with the photoelectric conversion element, wherein the threshold voltage of the third MOS transistor is set higher than that of the second MOS transistor. In one embodiment, each of the pixels included in a second group of rows includes a photoelectric conversion element but without the first, second and third MOS transistors. A fourth MOS transistor connects a photoelectric conversion element of the second group to a photoelectric conversion element of a first group, the photoelectric conversion elements of the first group being part of pixels which contain first, second and third MOS transistors.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: July 23, 1996
    Assignees: Nippon Hoso Kyokai, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumihiko Andoh, Kazuhisa Taketoshi, Katsu Tanaka, Masao Yamawaki, Hidekazu Yamamoto, Hiroshi Kawashima, Naofumi Murata
  • Patent number: 5466613
    Abstract: A camera device having favorable multiplication characteristics (quantum efficiency) as well as improved sensitivity in a visible light region (especially the region on the red side) and a method of manufacturing the same are provided. The camera device includes a hole injection stop layer, a first photoelectric converting layer including selenium, a second photoelectric converting layer having spectral sensitivity characteristics which are different from those of the first photoelectric converting layer, a third photoelectric converting layer including selenium, and an electron injection stop layer. As a result, it is possible to improve multiplication characteristics (quantum efficiency) and to improve the sensitivity in the visible light region (especially the region on the red side) simultaneously.
    Type: Grant
    Filed: January 10, 1995
    Date of Patent: November 14, 1995
    Assignees: Nippon Hoso Kyokai, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumihiko Andoh, Kazunori Miyakawa, Hidekazu Yamamoto, Masao Yamawaki
  • Patent number: 5399882
    Abstract: A camera device having favorable multiplication characteristics (quantum efficiency) as well as improved sensitivity in a visible light region (especially the region on the red side) and a method of manufacturing the same are provided. The camera device includes a hole injection stop layer, a first photoelectric converting layer including selenium, a second photoelectric converting layer having spectral sensitivity characteristics which are different from those of the first photoelectric converting layer, a third photoelectric converting layer including selenium, and an electron injection stop layer. As a result, it is possible to improve multiplication characteristics (quantum efficiency) and to improve the sensitivity in the visible light region (especially the region on the red side) simultaneously.
    Type: Grant
    Filed: June 16, 1993
    Date of Patent: March 21, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumihiko Andoh, Kazunori Miyakawa, Hidekazu Yamamoto, Masao Yamawaki
  • Patent number: 5371397
    Abstract: A solid-state imaging device includes a semiconductor substrate in which an element part including a plurality of light responsive elements for generating charge carriers in response to incident light and a transfer part for transferring the charge carriers generated in each light responsive element are incorporated; a lens layer is disposed on the element part so that incident light is collected in the light responsive elements; and a light beam dispersion layer is disposed between the lens layer and the element part and includes two light transmissive layers having different refractive indices for dispersing light collected by the lens layer so that collected light entering respective light responsive elements is closer to a parallel beam than the incident light. By suppressing broadening of incident light in the semiconductor substrate at the light responsive elements, fewer charge carriers enter the CCD channel region and smear is reduced.
    Type: Grant
    Filed: February 16, 1993
    Date of Patent: December 6, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeto Maegawa, Hidekazu Yamamoto, Hiroshi Kawashima
  • Patent number: 5311038
    Abstract: An improved photoelectric converter with reduced dark current includes a first electrode on a substrate covered by a semiconductor layer for photoelectric conversion. A second electrode is disposed on the semiconductor layer. An electron injection preventive layer is inserted between the semiconductor layer and the second electrode for preventing electrons from being injected from the second electrode into the semiconductor layer. The electron injection preventive layer is formed of a material satisfying the inequality:.phi..sub.M -x.sub.2 .gtoreq.Eg.sub.1where the work function of the second electrode is .phi..sub.M, the electron affinity of the electron injection preventive layer is x.sub.2, and the band gap energy of the semiconductor layer is Eg.sub.1.
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: May 10, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hidekazu Yamamoto, Yasutaka Nishioka
  • Patent number: 5238864
    Abstract: A method for producing a solid-state imaging device including a photodetector including implanting two different dopant impurity ions, each producing the second conductivity type and having different diffusion coefficients in a first conductivity type semiconductor layer; thermally diffusing the implanted ions to produce a second conductivity type region including a relatively deep second conductivity type subregion and a relatively shallow second conductivity type region having a higher dopant impurity concentration than said relatively deep second conductivity type subregion; forming a charge transfer electrode on said semiconductor layer such that an edge of said electrode lies adjacent part of the junction between said semiconductor layer and said second conductivity type region; and implanting a dopant impurity producing the first conductivity type in said second relatively shallow second conductivity type subregion using said charge transfer electrode as a mask to produce a first conductivity type impur
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: August 24, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeto Maegawa, Kiyohiko Sakakibara, Hidekazu Yamamoto
  • Patent number: 5191399
    Abstract: A solid-state imaging device includes a photodetector having a first conductivity type semiconductor layer, a second conductivity type semiconductor region in the layer, and a first conductivity type region in the second conductivity type region. The second conductivity type semiconductor region includes second conductivity type subregions having different dopant impurity concentrations. The subregion which contacts the first conductivity type region has a dopant impurity concentration higher than the second conductivity type subregion. The device reads out photogenerated charges stored in the second conductivity type region as a light signal. The junction capacitances between the second conductivity type semiconductor region and the first conductivity type layer and the first conductivity type region are increased so that the maximum quantity of stored charge when the first conductivity type region is depleted is increased without a change in the potential.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: March 2, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigeto Maegawa, Kiyohiko Sakakibara, Hidekazu Yamamoto
  • Patent number: 5040038
    Abstract: A solid-state image sensor comprises photoelectric converting devices (22) formed on a p type semiconductor substrate (1), transfer gates (26) for reading signal charges therefrom, scanning lines (21) for selecting the transfer gates (26), and transfer electrodes (11) of the first layer and transfer electrodes (12) of the second layer alternately disposed for transferring in the vertical direction the read signal charges. All the electrodes of the transfer gates (26) are formed integrally with the transfer electrodes (12) of the second layer, with the result that all the electrodes of the transfer gates (26) are common to the transfer electrodes of the same layer (the second layer). Although the potential wall (340) is formed in the transfer channel (3) beneath the transfer electrode (12) connected to the transfer gate (26), the same is insulated from adjacent the transfer electrode (11) on the charge transfer direction side.
    Type: Grant
    Filed: October 24, 1988
    Date of Patent: August 13, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Naoki Yutani, Sotoju Asai, Shiro Hine, Satoshi Hirose, Hidekazu Yamamoto, Masashi Ueno