Patents by Inventor Hideki Iwaki

Hideki Iwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7350175
    Abstract: The design system, which is equipped with capability to analyze circuit board design data, comprises a storing section for recording design data, including structure data, circuit data, and element data; a selection section for selecting a pair of circuit elements subject to interference analysis among circuit elements placed on a circuit board, represented by the structure data; a substitution section for acquiring element data concerning circuit elements selected by the selection section from the design data and, based on element data, generating equivalent circuit data representing electromagnetic coupling within the pair of circuit elements with the help of an equivalent circuit; and an analysis section for calculating an amount of interference within the pair of circuit elements by analyzing data produced by combining the equivalent circuit data with the circuit data.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: March 25, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Yukinobu Furukawa
  • Patent number: 7346051
    Abstract: A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements. Here, the master device includes command transmission unit configured to input an identification command to a terminal of an adjacent slave device.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: March 18, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takeshi Nakayama, Eiji Takahashi, Yoshiyuki Saito, Yukihiro Ishimaru, Hideki Iwaki
  • Patent number: 7061100
    Abstract: A semiconductor built-in millimeter-wave band module includes: an insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a high thermal conductivity substrate made of a dielectric material having thermal conductivity higher than the insulating substrate and laminated on one surface of the insulating substrate; a plurality of wiring patterns formed on the high thermal conductivity substrate and the insulating substrate; a semiconductor device operating at millimeter-wave band, which is arranged inside of the insulating substrate, is packaged on the high thermal conductivity substrate in a face-up manner, and is connected electrically with the wiring patterns; and a distributed constant circuit element and an active element provided on the semiconductor device. In this module, a void is provided inside of the insulating substrate and in the vicinity of a surface of the distributed constant circuit element and the active element.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: June 13, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyosi Ogura, Yasuhiro Sugaya, Toshiyuki Asahi, Tousaku Nishiyama, Yoshinobu Idogawa
  • Publication number: 20060070015
    Abstract: The design system, which is equipped with capability to analyze circuit board design data, comprises a storing section for recording design data, including structure data, circuit data, and element data; a selection section for selecting a pair of circuit elements subject to interference analysis among circuit elements placed on a circuit board, represented by the structure data; a substitution section for acquiring element data concerning circuit elements selected by the selection section from the design data and, based on element data, generating equivalent circuit data representing electromagnetic coupling within the pair of circuit elements with the help of an equivalent circuit; and an analysis section for calculating an amount of interference within the pair of circuit elements by analyzing data produced by combining the equivalent circuit data with the circuit data.
    Type: Application
    Filed: September 28, 2005
    Publication date: March 30, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Yukinobu Furukawa
  • Publication number: 20050289269
    Abstract: A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements. Here, the master device includes command transmission unit configured to input an identification command to a terminal of an adjacent slave device.
    Type: Application
    Filed: June 10, 2005
    Publication date: December 29, 2005
    Inventors: Takeshi Nakayama, Eiji Takahashi, Yoshiyuki Saito, Yukihiro Ishimaru, Hideki Iwaki
  • Publication number: 20050197817
    Abstract: An interference analysis device can be provided, which analyzes interference between wirings of a circuit board with reduced load and for a short time period. The interference analysis device according to the present invention includes: a design data input part for inputting design data of the circuit board; a noise characteristics setting part that sets data representing electrical characteristics of noise for a wiring of the circuit board; a limit value setting part that sets an allowable limit value of noise received by a wiring; a selection part that selects a wiring group to be analyzed based on the noise characteristics data and the allowable limit value; an interference analysis part that calculates, concerning the selected wiring group, an amount of interference from a wiring giving the interference to a wiring receiving the interference; and a received noise level calculation part that calculates a noise level that the wiring receiving the interference will receive.
    Type: Application
    Filed: March 8, 2005
    Publication date: September 8, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Tetsuyoshi Ogura, Naoki Komatsu, Takeshi Nakayama, Tomohiro Kinoshita
  • Patent number: 6885788
    Abstract: A light reception/emission device built-in module with optical and electrical wiring combined therein includes: an optical waveguide layer including a core portion and a cladding portion; first and second wiring patterns formed on a main surface of the optical waveguide layer; a light reception device disposed inside the optical waveguide layer, the light reception device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the first wiring pattern; and a light emission device disposed inside the optical waveguide layer, the light emission device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the second wiring pattern. With this configuration, optical coupling between the optical waveguide and the light reception/emission device can be conducted precisely.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: April 26, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyoshi Ogura, Yasuhiro Sugaya, Toshiyuki Asahi, Tousaku Nishiyama, Yoshinobu Idogawa
  • Patent number: 6870264
    Abstract: An insulator is provided between interconnect layers oppositely placed. The interconnect layers are connected between by connection members provided through the insulator. The connection members at one and the other ends are connected between in their center positions. A shield layer is provided spaced from the intermediate connection layer generally on a same plane as the intermediate connection layer. A condition of (R·r)/(2·h)?L?(5·R·r)/h is satisfied, provided that a connection distance between the interconnect layers through the connection members and the intermediate connection layer is h, the connection members where considered generally as a circular cylinder have a diameter R, the intermediate connection layer where considered generally as circular has a diameter r, and a spaced distance between the intermediate connection layer and the shield layer is L. Thus, characteristic impedance is stabilized.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: March 22, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyoshi Ogura
  • Patent number: 6789956
    Abstract: An optical module of the present invention is provided with a substrate that includes an insulating layer, a passive element provided inside or on the surface of the insulating layer, and terminal electrodes formed on the surface of the insulating layer, and with at least one active element, which includes at least an optical element and is connected to the terminal electrodes on the substrate surface. The passive element has a dielectric layer, a resistive layer, or a magnetic layer, at least one of the terminal electrodes is connected to the passive element, and at least one of the at least one active element has a protruding electrode and is flip-chip mounted to the terminal electrodes on a principle face of the substrate via the protruding electrode.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 14, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyosi Ogura
  • Publication number: 20040001661
    Abstract: A light reception/emission device built-in module with optical and electrical wiring combined therein includes: an optical waveguide layer including a core portion and a cladding portion; first and second wiring patterns formed on a main surface of the optical waveguide layer; a light reception device disposed inside the optical waveguide layer, the light reception device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the first wiring pattern; and a light emission device disposed inside the optical waveguide layer, the light emission device being optically connected with the core portion of the optical waveguide layer and being electrically connected with the second wiring pattern. With this configuration, optical coupling between the optical waveguide and the light reception/emission device can be conducted precisely.
    Type: Application
    Filed: June 20, 2003
    Publication date: January 1, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyoshi Ogura, Yasuhiro Sugaya, Toshiyuki Asahi, Tousaku Nishiyama, Yoshinobu Idogawa
  • Publication number: 20030189246
    Abstract: A semiconductor built-in millimeter-wave band module includes: an insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a high thermal conductivity substrate made of a dielectric material having thermal conductivity higher than the insulating substrate and laminated on one surface of the insulating substrate; a plurality of wiring patterns formed on the high thermal conductivity substrate and the insulating substrate; a semiconductor device operating at millimeter-wave band, which is arranged inside of the insulating substrate, is packaged on the high thermal conductivity substrate in a face-up manner, and is connected electrically with the wiring patterns; and a distributed constant circuit element and an active element provided on the semiconductor device. In this module, a void is provided inside of the insulating substrate and in the vicinity of a surface of the distributed constant circuit element and the active element.
    Type: Application
    Filed: April 2, 2003
    Publication date: October 9, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyosi Ogura, Yasuhiro Sugaya, Toshiyuki Asahi, Tousaku Nishiyama, Yoshinobu Idogawa
  • Publication number: 20030123815
    Abstract: An optical module of the present invention is provided with a substrate that includes an insulating layer, a passive element provided inside or on the surface of the insulating layer, and terminal electrodes formed on the surface of the insulating layer, and with at least one active element, which includes at least an optical element and is connected to the terminal electrodes on the substrate surface. The passive element has a dielectric layer, a resistive layer, or a magnetic layer, at least one of the terminal electrodes is connected to the passive element, and at least one of the at least one active element has a protruding electrode and is flip-chip mounted to the terminal electrodes on a principle face of the substrate via the protruding electrode.
    Type: Application
    Filed: December 19, 2002
    Publication date: July 3, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyosi Ogura
  • Patent number: 6537855
    Abstract: A first bump and a second bump are formed on the surface of a mounting board (substrate) so that the second bump is allowed to be higher than the first bump. A conductive adhesive member is transferred onto those bumps. A semiconductor substrate in which a mesa portion has been processed is mounted on the mounting board so that the first bump does not come into contact with an electrode on a top of the mesa portion directly while electrically connected to the electrode via the conductive adhesive member. In the semiconductor device in which the semiconductor substrate is mounted with an active surface processed to form the mesa portion facing the mounting board, the stresses applied to the mesa portion (a stress caused in mounting and a stress due to a heat cycle in use) are relieved, thus preventing deterioration of an element.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: March 25, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yutaka Taguchi, Tetsuyosi Ogura, Hideki Iwaki
  • Publication number: 20020180063
    Abstract: At least four terminal electrodes are provided on a surface of multi-layer substrate main body. An electric functional layer is selectively provided at an internal area of said multi-layer substrate placed at a downward position of all terminal electrodes in a substrate thickness direction. A semiconductor device is flip-chip-bonded to the terminal electrodes. Thus, the semiconductor device is electrically connected to the electric functional layer at a short distance. As a result, a reduction in parasitic inductance and an improvement in high frequency characteristic can be accomplished. Generation of height variations between the terminal electrodes can be prevented, and the semiconductor device is stably flip-chip-bonded to the multi-layer substrate.
    Type: Application
    Filed: June 5, 2002
    Publication date: December 5, 2002
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Tetsuyoshi Ogura, Yutaka Taguchi
  • Patent number: 6392164
    Abstract: An insulator is provided between interconnect layers oppositely placed. The interconnect layers are connected between by connection members provided through the insulator. The connection members at one and the other ends are connected between in their center positions. A shield layer is provided spaced from the intermediate connection layer generally on a same plane as the intermediate connection layer. The interconnect layers where considered generally as a circular cylinder have a diameter m, and the intermediate connection layer where considered generally as circular has a diameter r, r<m is given where the connection members are high in characteristic impedance than the interconnect layers, and r<m is given where the connection members are low in characteristic impedance then the interconnect layers.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: May 21, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyoshi Ogura
  • Publication number: 20020034839
    Abstract: An insulator is provided between interconnect layers oppositely placed. The interconnect layers are connected between by connection members provided through the insulator. The connection members at one and the other ends are connected between in their center positions. A shield layer is provided spaced from the intermediate connection layer generally on a same plane as the intermediate connection layer. A condition of (R·r)/(2·h)≦L≦(5·R·r)/h is satisfied, provided that a connection distance between the interconnect layers through the connection members and the intermediate connection layer is h, the connection members where considered generally as a circular cylinder have a diameter R, the intermediate connection layer where considered generally as circular has a diameter r, and a spaced distance between the intermediate connection layer and the shield layer is L. Thus, characteristic impedance is stabilized.
    Type: Application
    Filed: November 28, 2001
    Publication date: March 21, 2002
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hideki Iwaki, Yutaka Taguchi, Tetsuyoshi Ogura
  • Patent number: 6348739
    Abstract: A first bump and a second bump are formed on the surface of a mounting board (substrate) so that the second bump is allowed to be higher than the first bump. A conductive adhesive member is transferred onto those bumps. A semiconductor substrate in which a mesa portion has been processed is mounted on the mounting board so that the first bump does not come into contact with an electrode on a top of the mesa portion directly while electrically connected to the electrode via the conductive adhesive member. In the semiconductor device in which the semiconductor substrate is mounted with an active surface processed to form the mesa portion facing the mounting board, the stresses applied to the mesa portion (a stress caused in mounting and a stress due to a heat cycle in use) are relieved, thus preventing deterioration of an element.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: February 19, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yutaka Taguchi, Tetsuyosi Ogura, Hideki Iwaki
  • Patent number: 6310393
    Abstract: The semiconductor package of this invention includes: a semiconductor element having a power supply terminal, a ground terminal, and an output terminal; an inductance; and a capacitance. One of opposing terminals of the capacitance is connected to the power supply terminal of the semiconductor element, and the other terminal is connected to the ground terminal of the semiconductor element. The ground terminal of the semiconductor element is connected to a ground terminal of the semiconductor package, the power supply terminal of the semiconductor element is connected to a power supply terminal of the semiconductor package via the inductance, and the output terminal of the semiconductor element is connected to an output terminal of the semiconductor package.
    Type: Grant
    Filed: October 5, 1999
    Date of Patent: October 30, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuyosi Ogura, Yukihiro Fukumoto, Hideki Iwaki, Yutaka Taguchi, Yoshihiro Bessho
  • Publication number: 20010019173
    Abstract: A first bump and a second bump are formed on the surface of a mounting board (substrate) so that the second bump is allowed to be higher than the first bump. A conductive adhesive member is transferred onto those bumps. A semiconductor substrate in which a mesa portion has been processed is mounted on the mounting board so that the first bump does not come into contact with an electrode on a top of the mesa portion directly while electrically connected to the electrode via the conductive adhesive member. In the semiconductor device in which the semiconductor substrate is mounted with an active surface processed to form the mesa portion facing the mounting board, the stresses applied to the mesa portion (a stress caused in mounting and a stress due to a heat cycle in use) are relieved, thus preventing deterioration of an element.
    Type: Application
    Filed: April 5, 2001
    Publication date: September 6, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yutaka Taguchi, Tetsuyosi Ogura, Hideki Iwaki
  • Patent number: 6154940
    Abstract: The present invention relates to an electronic part used for mobile communications apparatuses and the like, and more particularly to an electronic part, such as an acoustic surface-wave device, a piezoelectric ceramic device or the like, which requires an oscillation space near the surface of the functional device chip thereof, and a method of production thereof. With this method, a space retainer for forming a sealed space at the functional portion of the chip can be hermetically sealed and have high moisture resistance, and the process of forming the space retainer can be carried out easily.
    Type: Grant
    Filed: June 3, 1998
    Date of Patent: December 5, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiji Onishi, Hideki Iwaki, Shun-ichi Seki, Yutaka Taguchi, Tsukasa Shiraishi, Yoshihiro Bessho, Osamu Kawasaki, Kazuo Eda