Patents by Inventor Hideki Kanayama

Hideki Kanayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230102680
    Abstract: A memory controller includes a command queue with multiple entry stacks, each with a plurality of entries holding memory access commands, one or more parameter indicators each holding a respective characteristic common to the plurality of entries, and a head indicator designating a current entry for arbitration. An arbiter has a single command input for each entry stack. A command queue loader circuit receives incoming memory access commands and loads entries of respective entry stacks with memory access commands having the respective characteristic of each of the one or more parameter indicators in common.
    Type: Application
    Filed: September 30, 2021
    Publication date: March 30, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Hideki Kanayama, Eric M. Scott
  • Publication number: 20230004400
    Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.
    Type: Application
    Filed: September 13, 2022
    Publication date: January 5, 2023
    Inventors: JYOTI RAHEJA, HIDEKI KANAYAMA, GUHAN KRISHNAN, RUIHUA PENG
  • Patent number: 11449346
    Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: September 20, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jyoti Raheja, Hideki Kanayama, Guhan Krishnan, Ruihua Peng
  • Publication number: 20210191737
    Abstract: A system for providing system level sleep state power savings includes a plurality of memory channels and corresponding plurality of memories coupled to respective memory channels. The system includes one or more processors operative to receive information indicating that a system level sleep state is to be entered and in response to receiving the system level sleep indication, moves data stored in at least a first of the plurality of memories to at least a second of the plurality of memories. In some implementations, in response to moving the data to the second memory, the processor causes power management logic to shut off power to: at least the first memory, to a corresponding first physical layer device operatively coupled to the first memory and to a first memory controller operatively coupled to the first memory and place the second memory in a self-refresh mode of operation.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 24, 2021
    Inventors: Jyoti Raheja, Hideki Kanayama, Guhan Krishnan, Ruihua Peng
  • Patent number: 10684969
    Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 16, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan, Jackson Peng, Hideki Kanayama
  • Patent number: 10403333
    Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: September 3, 2019
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Kevin M. Brandl, Thomas Hamilton, Hideki Kanayama, Kedarnath Balakrishnan, James R. Magro, Guanhao Shen, Mark Fowler
  • Publication number: 20180018291
    Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 18, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: James R. Magro, Kedarnath Balakrishnan, Jackson Peng, Hideki Kanayama
  • Publication number: 20180019006
    Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.
    Type: Application
    Filed: July 15, 2016
    Publication date: January 18, 2018
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Kevin M. Brandl, Thomas Hamilton, Hideki Kanayama, Kedarnath Balakrishnan, James R. Magro, Guanhao Shen, Mark Fowler
  • Patent number: 6147633
    Abstract: In a delta-sigma type analog-to-digital converter, an offset varying during operation is removed, and a reduction in time required to generate a stable value after powering on the converter is achieved. A high pass filter is provided with a variable filter coefficient which can vary during operation. A filter coefficient controller supplies a coefficient control signal to the high pass filter to change the variable filter coefficient during operation, thereby altering the time constant of the high pass filter.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: November 14, 2000
    Assignee: Burr-Brown Corporation
    Inventors: Masayuki Ukawa, Hideki Kanayama
  • Patent number: 5835038
    Abstract: A characteristic tone in a delta-sigma analog-to-digital converter is shifted out of an audible pass band without diminishing dynamic range or signal-to-noise ratio thereof by operating the digital-to-analog converter to measure its offset voltage. If the amplitude of the measured offset voltage exceeds a predetermined value, no dither signal is applied to the input of the delta-sigma modulator. If the measured offset voltage is less than the predetermined value, a positive DC dither voltage is added to the input voltage of the delta-sigma modulator if the measured offset voltage is positive, or is subtracted if the measured offset voltage is negative.
    Type: Grant
    Filed: May 8, 1997
    Date of Patent: November 10, 1998
    Assignee: Burr-Brown Corporation
    Inventors: Shigetoshi Nakao, Hideki Kanayama, Toshio Murota, Masayuki Ukawa