Patents by Inventor Hideki Makiyama

Hideki Makiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200013857
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
  • Patent number: 10461158
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: October 29, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Patent number: 10446401
    Abstract: Reliability of a semiconductor device is improved. In a method of manufacturing a semiconductor device, nitrogen is introduced into a surface of a substrate and a sacrificial film is formed on the surface in a field effect transistor formation region different from a memory transistor formation region. Subsequently, the sacrificial film is removed to remove the nitrogen introduced in the surface of the substrate in the field effect transistor formation region.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 15, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Makiyama
  • Patent number: 10419631
    Abstract: An image forming apparatus includes an image display that displays an image. In response to determining both that the image display is present in a detected user's gaze direction and that a distance between the user and the image display is shorter than a predetermined distance, the apparatus performs a change process on the image. After performing the change process, the apparatus determines whether or not the distance between the user and the image display is equal to or greater than the predetermined distance, and if so, returns the image back to a state prior to the change process.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 17, 2019
    Assignee: FUJI XEROX CO., LTD.
    Inventors: Kensuke Okamoto, Yoshifumi Bando, Yuichi Kawata, Hideki Yamasaki, Ryoko Saitoh, Tomoyo Nishida, Mayumi Makiyama
  • Patent number: 10366914
    Abstract: In a manufacturing method for a semiconductor device formed over an SOI substrate, a first epitaxial layer is partially formed over an outer circumference end of a first semiconductor layer in a wide active region. Then, a second epitaxial layer is formed over each of the first semiconductor layers in a narrow active region and the wide active region. Thereby, a second semiconductor layer configured by a laminated body of the first semiconductor layer and the first and second epitaxial layers is formed in the wide active region and a third semiconductor layer configured by a laminated body of the first semiconductor layer and the second epitaxial layer is formed in the narrow active region.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: July 30, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hideki Makiyama
  • Patent number: 10325899
    Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: June 18, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keiichi Maekawa, Hideaki Yamakoshi, Shinichiro Abe, Hideki Makiyama, Tetsuya Yoshida, Yuto Omizu
  • Publication number: 20190164764
    Abstract: Reliability of a semiconductor device is improved. In a method of manufacturing a semiconductor device, nitrogen is introduced into a surface of a substrate and a sacrificial film is formed on the surface in a field effect transistor formation region different from a memory transistor formation region. Subsequently, the sacrificial film is removed to remove the nitrogen introduced in the surface of the substrate in the field effect transistor formation region.
    Type: Application
    Filed: September 12, 2018
    Publication date: May 30, 2019
    Inventor: Hideki MAKIYAMA
  • Patent number: 10297613
    Abstract: Reliability of a semiconductor device is improved. Prepared is a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed by using a first etching liquid; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned by using a second etching liquid different from the first etching liquid. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed. An etching speed of each of the insulating film and the insulating layer due to the first etching liquid is smaller than an etching speed of the semiconductor layer by using the first etching liquid.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 21, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Hideki Makiyama
  • Patent number: 10263012
    Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: April 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki Makiyama, Yoshiki Yamamoto
  • Patent number: 10263078
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Publication number: 20190043949
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Application
    Filed: October 3, 2018
    Publication date: February 7, 2019
    Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
  • Publication number: 20180350844
    Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.
    Type: Application
    Filed: July 19, 2018
    Publication date: December 6, 2018
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki MAKIYAMA, Yoshiki YAMAMOTO
  • Publication number: 20180286850
    Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.
    Type: Application
    Filed: January 25, 2018
    Publication date: October 4, 2018
    Inventors: Keiichi Maekawa, Hideaki Yamakoshi, Shinichiro Abe, Hideki Makiyama, Tetsuya Yoshida, Yuto Omizu
  • Publication number: 20180247861
    Abstract: In a manufacturing method for a semiconductor device formed over an SOI substrate, a first epitaxial layer is partially formed over an outer circumference end of a first semiconductor layer in a wide active region. Then, a second epitaxial layer is formed over each of the first semiconductor layers in a narrow active region and the wide active region. Thereby, a second semiconductor layer configured by a laminated body of the first semiconductor layer and the first and second epitaxial layers is formed in the wide active region and a third semiconductor layer configured by a laminated body of the first semiconductor layer and the second epitaxial layer is formed in the narrow active region.
    Type: Application
    Filed: January 3, 2018
    Publication date: August 30, 2018
    Inventor: Hideki MAKIYAMA
  • Patent number: 10056406
    Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: August 21, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki Makiyama, Yoshiki Yamamoto
  • Publication number: 20180226431
    Abstract: Reliability of a semiconductor device is improved. Prepared is a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed by using a first etching liquid; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned by using a second etching liquid different from the first etching liquid. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed. An etching speed of each of the insulating film and the insulating layer due to the first etching liquid is smaller than an etching speed of the semiconductor layer by using the first etching liquid.
    Type: Application
    Filed: April 2, 2018
    Publication date: August 9, 2018
    Applicant: Renesas Electronics Corporation
    Inventor: Hideki MAKIYAMA
  • Publication number: 20180219067
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Application
    Filed: March 20, 2018
    Publication date: August 2, 2018
    Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
  • Patent number: 10014385
    Abstract: The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an offset spacer film formed over the side wall surface of a gate electrode of an SOTB transistor STR, etc. When the measured thickness is within the tolerance of a standard thickness, standard implantation energy and a standard dose amount are set. When the measured thickness is smaller than the standard thickness, implantation energy and a dose amount, which are respectively lower than the standard values thereof, are set. When the measured thickness is larger than the standard thickness, implantation energy and a dose amount, which are respectively higher than the standard values thereof, are set.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: July 3, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hideki Makiyama
  • Patent number: 9978839
    Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: May 22, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
  • Patent number: 9960183
    Abstract: A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: May 1, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Hideki Makiyama