Abstract: Provided is a color reproduction system that prevents differences in display image coloring due to a primary device and can also be produced more easily than when using conventional technologies. The color reproduction system includes: an electronic device that includes an input data converter that performs a color gamut conversion process to input data (DIN) in accordance with the color gamut of the input data (DIN) and a color gamut specified by a prescribed standard (such as sRGB or bg-sRGB); and a liquid crystal display device that includes an image data converter and a liquid crystal panel. The image data converter performs a color gamut conversion process on image data (DAT) sent from the electronic device in accordance with the color gamut specified by the prescribed standard and the color gamut of the liquid crystal panel, and the liquid crystal panel displays an image using the image data (DAT).

Abstract: A liquid crystal display device capable of reproducing colors faithfully is provided. The liquid crystal display device includes a color gamut conversion unit that generates an RGB signal for a liquid crystal panel (RGBout), which is provided to a liquid crystal panel, by converting data values of respective colors included in an input RGB signal (RGBin) in accordance with the color gamut of the input RGB signal (RGBin) and the color gamut of the liquid crystal panel. When the color gamut of the input RGB signal (RGBin) is included within the color gamut of the liquid crystal panel, colors represented by the input RGB signal (RGBin) are faithfully reproduced on the liquid crystal panel by providing the RGB signal for liquid crystal panel generated by the color gamut conversion unit to the liquid crystal panel.

Abstract: Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device. In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged.

Abstract: The invention provides a liquid crystal display device that includes an IGZO-GDM which can quickly remove a residual charge in a panel when the power supply is turned off, and a driving method of the liquid crystal display device. Each bistable circuit that configures a shift register includes a thin film transistor TI for increasing a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin film transistor TI, a thin film transistor TC for lowering a potential of the region netA, and a region netB connected to a gate terminal of the thin film transistor TC. In such a configuration, a power supply off sequence includes a display off sequence and a gate off sequence. The gate off sequence includes at least a gate-bus-line discharge step (t14 to t15), a netB discharge step (t15 to t16), and a netA discharge step (t16 to t17).

Abstract: A backlight device that achieves high efficiency for a plurality of input voltages includes: a converter circuit; a first light-emitting element column and a second light-emitting element column each including one or more light-emitting elements connected in series; and a group of switches configured to control electrical connection between the converter circuit, the first light-emitting element column and the second light-emitting element column, wherein the group of switches are switched between a plurality of connection states including a first connection state in which the first light-emitting element column and the second light-emitting element column are in series and connected with the converter circuit and a second connection state in which the first light-emitting element column and the second light-emitting element column are in parallel and connected with the converter circuit.

Abstract: The liquid crystal display device includes a liquid crystal panel including a display area for displaying images and a non-display area other than the display area, a rigid board configured to connect with an external signal source, and a flexible board. The liquid crystal panel and the flexible board are arranged in a first direction. A direction perpendicular to the first direction and along a plate surface of the liquid crystal panel is a second direction. The flexible board is larger in a dimension in the second direction than the rigid board, and includes an end portion including at least an outer portion located outside of the rigid board in the second direction, and a middle portion located about a middle of the flexible board with respect to the end portion in the second direction. The end portion is larger in dimension in the first direction than the middle portion.

Abstract: A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts.

Abstract: Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device. In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged.

Abstract: The invention provides a liquid crystal display device that includes an IGZO-GDM which can quickly remove a residual charge in a panel when the power supply is turned off, and a driving method of the liquid crystal display device. Each bistable circuit that configures a shift register includes a thin film transistor TI for increasing a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin film transistor TI, a thin film transistor TC for lowering a potential of the region netA, and a region netB connected to a gate terminal of the thin film transistor TC. In such a configuration, a power supply off sequence includes a display off sequence and a gate off sequence. The gate off sequence includes at least a gate-bus-line discharge step (t14 to t15), a netB discharge step (t15 to t16), and a netA discharge step (t16 to t17).

Abstract: A display device, in at least one embodiment, includes: a gate driver including a plurality of shift register stages each provided so as to correspond to each row, the gate driver outputting a gate signal for turning on switching elements in the each row; and a source driver outputting a data signal in accordance with an image to be displayed. For a row (first row) located at an outermost position from which scanning by use of the gate signal starts, a dummy line is provided. The dummy line is driven by a gate start pulse inputted into a shift register in the first row.

Abstract: In one embodiment of the present invention, in an even-numbered signal line group, the arrangement sequence of the first and second signal lines is reversed between in a display area and in a non-display area, and the same goes for the arrangement sequence of the third and fourth signal lines. The ends of the first to sixteenth signal lines in the non-display area are connected to the first to sixteenth individual drivers, respectively. An odd-numbered individual driver and an even-numbered individual driver each output a corresponding one of drive signals of opposite polarity. Thus, the polarities of subpixels of the same color arranged in a first direction D1 (horizontal direction) differ between the subpixels connected to the odd-numbered signal line group and the subpixels connected to the even-numbered signal line group. That is, all of the subpixels having the same color arranged in the horizontal direction do not have the same polarity. This helps reduce a horizontal shadow.

Abstract: An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver. In a shift register (410) that operates based on four-phase clock signals, including two-phase clock signals (GCK1, GCK3) that are provided to odd-order stages and two-phase clock signals (GCK2, GCK4) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

Abstract: Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

Abstract: A liquid crystal display device includes: scanning wires, provided so as to correspond to a plurality of pixels disposed in a matrix manner, to which scanning signals are applied; and signal wires to which data signals are applied, wherein the scanning wires and the signal wires cross each other. TFTs, electrically connected to the scanning wires and the signal wires, each of which is provided in the vicinity of an intersection of the scanning wire and the signal wire, and the TFTs are connected to pixel electrodes. A dummy pixel driven by a dummy signal wire is provided externally adjacent to an endmost pixel column. This brings about a matrix type liquid crystal display device that equalizes capacitive conditions of all the signal wires to each other and can prevent deterioration of display quality that is brought about by a specific portion differently displayed.

Abstract: The present invention provides a display panel having decreased cost and current consumption by decreasing the number of data signal lines from the conventional number, a display device including the display panel, and a method of driving the display device. Each pixel formation portion (10) included in a display unit (200) of a display device is configured to arrange three sub-pixel formation portions (1r, 1g, 1b) for forming sub-pixels of mutually different color components in a data signal line extension direction. Each one data signal line (30) is arranged between a sub-pixel formation portion vertical string (3) in an odd-order from a front of a scanning signal line extension direction and a sub-pixel formation portion vertical string (3) adjacent to the sub-pixel formation portion vertical string (3) at the back of the scanning signal line extension direction. Sub-pixel formation portion vertical strings (3, 3) positioned at both sides of each data signal line (30) are connected to the data signal line.

Abstract: An object of the present invention is to provide a level shift IC with a reduced number of input signals over the conventional case. A level shift IC includes an amplitude converting unit including four level shifters; and a different-phase signal generating unit at a stage previous to the amplitude converting unit, including delay circuits. The different-phase signal generating unit generates, by the delay circuits, first and second delayed input signals from first and second input signals of different phases. Therefore, four input signals of different phases are obtained, and the amplitude converting unit increases the amplitudes of the input signals by the amplitude converting unit and thereby generates first to fourth output signals with different phases and increased amplitudes.

Abstract: An object is to provide at low cost a Power-supply circuit that can generate positive and negative analog power source voltages of which absolute values of voltage values are equal. A Power-supply circuit (210) is configured by a DCDC converter circuit (212) and a charge pump circuit (214). The charge pump circuit (214) includes a diode (D3) that passes a current when a control switch (51) is in an off state, and a diode (D4) that passes a current when the control switch (51) is in an on state. A DCDC converter circuit (212) includes two diodes (D1, D2) that pass a current when the control switch (S1) is in an off state. A rectifying unit that includes the diodes (D1, D2) is configured such that a forward drop voltage of the rectifying unit becomes equal to a sum of a forward drop voltage of the diode (D3) and a forward drop voltage of the diode (D4).

Abstract: A liquid crystal display device includes a monolithic gate driver capable of quickly eliminating residual charges within pixel formation portions when the power-supply is turned off. Each of bistable circuits that constitute a shift register within a gate driver is provided with a thin-film transistor having a drain terminal connected to a gate bus line, a source terminal connected to a reference potential line for transmitting a reference potential, and a gate terminal to which a clock signal for operating the shift register is supplied. When the external supply of power-supply voltage is cut off, the clock signal is set to high level to turn the thin-film transistor to the ON state, and the level of the reference potential is increased from a gate-OFF potential to a gate-ON potential.

Abstract: In one embodiment of the present invention, a video signal processing method is disclosed wherein video correction data is read from a ROM and written into an LUT, and the video correction data written in the LUT is used to perform data correction of an externally inputted video signal. The video correction data written in the LUT is updated during the horizontal blanking interval of the video signal.

Abstract: In a shift register that operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock appears as a potential of a scanning signal, when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.