Abstract: Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: Provided is a liquid crystal display device performing a precharge and having a function of switching an order for selecting scanning lines, in which such as flicker and burn-in can be prevented from being produced. A scanning line drive circuit selects scanning lines either in ascending order or in descending order based on an order of arrangement according to a shift direction signal, and causes selection periods of the scanning lines to be partially overlapped for a precharge. A data line drive circuit applies voltages of different polarities to data lines by frame and by data line. A common voltage generating circuit generates two types of voltages whose levels are independently adjustable, selects one of the two voltages according to a scan selection signal and applies the selected voltage to a common electrode of a liquid crystal panel. As the common voltage generating circuit, a D/A converter may be used.

Abstract: A display device supplies, during a vertical blanking interval, a data signal for a gray display to each data signal line so as to cause the each data signal line to retain the data signal for the gray display. In at least one example embodiment, the data signal for the gray display has a polarity identical to a polarity of a data signal supplied immediately before the vertical blanking interval.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sxl in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: An LUT fixedly stores correction values to compensate for a pull-in voltage in pixels in a liquid crystal panel. In at least one example embodiment, the display control unit outputs an input video signal Xa, a video signal Xp of a previous frame read from a frame memory, and a pixel polarity indicating a polarity of a pixel applied voltage on the pixel basis, and outputs a correction value read from the LUT to a data line driving circuit as a video signal Xb after correction. The data line driving circuit performs alternate current driving, based on the video signal Xb after correction. The LUT stores different correction values between when a positive polarity voltage is applied and when a negative polarity voltage is applied, for at least a part of combinations of values of the input video signal Xa and the video signal Xp of the previous frame.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: In at least one embodiment, under a non-load condition of a first supply line for a first clock signal and a second supply line for a second clock signal, a fall time of a clock pulse of the first clock signal, which is supplied to the first supply line, is longer than that of the second clock signal, which is supplied to the second supply line.

Abstract: In a display device of the present invention, during a period until the start of outputting display data from a source driver, a timing control ASIC generates a gate start pulse signal GSP and a first pulse CK1 of a gate clock signal GCK, with reference to the timing of inputting a data enable signal ENAB. The signals having been generated are supplied to the gate driver, so that a dummy line G0 is driven.

Abstract: A control section prepares a control signal and supplies the control signal to a control terminal of a first switching element, the control signal causing the first switching element to turn on in accordance with a non-active voltage level of a storage node and an active voltage level of a second clock signal which active voltage level is obtained in a period in which the second clock signal is active.

Abstract: A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts.

Abstract: A display panel drive circuit including a shift register including unit circuits connected in cascade, each of the unit circuits outputting a signal line selection signal, is so configured that: each of the unit circuits receives a clock signal nd either a signal line selection signal outputted from another-stage unit circuit or a start pulse signal, and the clock signal has a returned portion following an activation portion thereof, the returned portion including a first region that is sloped and a second region that is sloped more steeply than the first region. With the configuration, it is possible to realize a display panel drive circuit and a display panel driving method each of which (i) restrains an occurrence of a poor gate-on pulse signal, (ii) improves a pixel charging rate, and (iii) allows a clock signal to have higher frequency.

Abstract: In at least one embodiment, each of stages connected in cascade includes a first circuit which causes a predetermined section in a corresponding one of the stages to be connected to a low-potential power source, the first circuit being constituted by TFTs, a first type of clock signal being used as a signal which is transferred to an output terminal of each of the stages so as to be outputted as an output signal, a second type of clock signal being used as a signal which drives the first circuit. With the arrangement, it is possible to realize a shift register circuit that is capable of further suppressing a shift phenomenon of a threshold voltage in each of the TFTs.

Abstract: Each stage of first and second shift registers outputs a scan pulse by transferring a clock pulse of a clock signal supplied through a first clock input terminal. A first transistor is provided in at least one embodiment so as to connect and disconnect a scan signal line corresponding to the individual stage to and from a low-level power source of the scan pulse, and the first transistor has a gate that receives a clock signal supplied through a second clock input terminal. Two clock signals supplied to the first shift register and two clock signals supplied to the second shift register are different from each other in timings of their clock pulses. This realizes a display device capable of curbing the phenomenon in which a threshold voltage of a sink-down transistor is shifted, while sinking the gate line voltage down.

Abstract: In at least one embodiment, a display panel drive circuit including a shift register including unit circuits connected in cascade, each of the unit circuits outputting a signal line selection signal, is configured such that: each of the unit circuits receives a clock signal and either a signal line selection signal outputted from another-stage unit circuit or a start pulse signal; and the clock signal has a rising portion which is caused by activation of the clock signal and which is sloped or a falling portion which is caused by activation of the clock signal and which is sloped. With the configuration, it is possible to realize a display panel drive circuit and a display panel driving method each of which hardly causes a poor gate-on pulse signal (which causes unevenness in electric potential during inactivation, for example.

Abstract: A display device, in at least one embodiment, includes: a gate driver including a plurality of shift register stages each provided so as to correspond to each row, the gate driver outputting a gate signal for turning on switching elements in the each row; and a source driver outputting a data signal in accordance with an image to be displayed. For a row (first row) located at an outermost position from which scanning by use of the gate signal starts, a dummy line is provided. The dummy line is driven by a gate start pulse inputted into a shift register in the first row.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: A liquid crystal display device includes: scanning wires, provided so as to correspond to a plurality of pixels disposed in a matrix manner, to which scanning signals are applied; and signal wires to which data signals are applied, wherein the scanning wires and the signal wires cross each other. TFTs, electrically connected to the scanning wires and the signal wires, each of which is provided in the vicinity of an intersection of the scanning wire and the signal wire, and the TFTs are connected to pixel electrodes. A dummy pixel driven by a dummy signal wire is provided externally adjacent to an endmost pixel column. This brings about a matrix type liquid crystal display device that equalizes capacitive conditions of all the signal wires to each other and can prevent deterioration of display quality that is brought about by a specific portion differently displayed.

Abstract: In the display device and the display method of the present invention, a scanning signal line driving circuit controls falls of a scanning signal line, so as to make level shifts occurring to pixel potentials substantially uniform throughout display plane, the level shifts being caused by parasitic capacitances which parasitically exist in scanning signal lines. Fall waveforms of the scanning signal change at a change rate Sx which is a change quantity per unit time, and by desirably setting the change rate Sx, a change rate Sx1 in the vicinity of an input-side end of the scanning signal line and a change rate SxN in the vicinity of the other end thereof are substantially equal to each other, not being influenced by signal delay transmission characteristic which the scanning signal line possesses, like scanning signal line waveforms Vg(1, j) and Vg(N, j).

Abstract: A liquid crystal display device includes: scanning wires, provided so as to correspond to a plurality of pixels disposed in a matrix manner, to which scanning signals are applied; and signal wires to which data signals are applied, wherein the scanning wires and the signal wires cross each other. TFTs, electrically connected to the scanning wires and the signal wires, each of which is provided in the vicinity of an intersection of the scanning wire and the signal wire, and the TFTs are connected to pixel electrodes. A dummy pixel driven by a dummy signal wire is provided externally adjacent to an endmost pixel column. This brings about a matrix type liquid crystal display device that equalizes capacitive conditions of all the signal wires to each other and can prevent deterioration of display quality that is brought about by a specific portion differently displayed.