Patents by Inventor Hideki Yagi

Hideki Yagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150129816
    Abstract: There is provided a rare-earth gallium garnet ceramic having a high extinction ratio and a high light transmittance. The rare-earth gallium garnet ceramic contains, as a sintering aid, 5 mass ppm or more and 500 mass ppm or less of Ge calculated as metal, and 20 mass ppm or more and 250 mass ppm or less of Al calculated as metal.
    Type: Application
    Filed: April 5, 2013
    Publication date: May 14, 2015
    Inventors: Hoshiteru Nozawa, Hideki Yagi, Takagimi Yanagitani
  • Patent number: 9023677
    Abstract: A method for producing a spot size converter includes the steps of forming a first insulator mask on a stacked semiconductor layer; forming first and second terraces, and a waveguide mesa disposed between the first and second terraces by etching the stacked semiconductor layer using the first insulator mask, the first terrace having first to fourth terrace portions, the second terrace having fifth to eighth terrace portions, the waveguide mesa having first to fourth mesa portions; forming a second insulator mask including a first pattern on the first terrace portion, a second pattern on the fifth terrace portion, a third pattern on the third and fourth mesa portions, and a fourth pattern that integrally covers a region extending from the fourth terrace portion to the eighth terrace portion through the fourth mesa portion; and selectively growing a semiconductor layer by using the second insulator mask.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: May 5, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naoko Konishi, Hideki Yagi, Ryuji Masuyama, Yoshihiro Yoneda
  • Patent number: 8986553
    Abstract: A method for manufacturing an optical semiconductor device includes the steps of preparing a substrate product including a semiconductor layer, a mesa structure, and a protective layer; forming a buried layer composed of a resin on the substrate product; forming a first opening in the buried layer on the mesa structure; forming a second opening in the buried layer on the semiconductor layer; exposing the mesa structure and the semiconductor layer by etching the protective layer; forming a first electrode in the first opening; and forming a second electrode in the second opening. The step of forming the second opening includes a first etching step including etching the buried layer using a first resist mask for forming a recess and a second etching step including etching the buried layer using a second resist mask having an opening pattern which has an opening width not smaller than that of the recess.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takamitsu Kitamura, Hideki Yagi
  • Patent number: 8986560
    Abstract: A method for producing an optical semiconductor device includes the steps of determining a wafer size to make a section arrangement including a plurality of sections in each of which the optical semiconductor device including a semiconductor mesa is formed; obtaining an in-plane distribution of a thickness of a resin layer on a wafer; obtaining a correlation between a thickness of a resin layer and a trench width; forming a trench width map using the in-plane distribution of the thickness and the correlation; preparing an epitaxial substrate by forming a stacked semiconductor layer; forming, on the epitaxial substrate, a mask based on the trench width map; forming a trench structure including the semiconductor mesa by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takamitsu Kitamura, Hideki Yagi
  • Patent number: 8969989
    Abstract: An optical-to-electrical converter unit includes a substrate having front and back surfaces; an original waveguide unit; and an optical-to-electrical converter. The optical-to-electrical converter includes a light-receiving element optically coupled to the optical waveguide unit; a capacitance element including first and second conductive layers and an insulating layer disposed between the first and second conductive layers; an electrode pad electrically connected to the light-receiving element; a back electrode formed on the back surface of the substrate; and a via electrode extending from the front surface to the back surface of the substrate. The optical waveguide unit, the light-receiving element, the capacitance element, and the electrode pad are formed on the front surface. The first conductive layer of the capacitance element is electrically connected to the light-receiving element and the electrode pad.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: March 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd
    Inventors: Yoshihiro Yoneda, Ryuji Masuyama, Hideki Yagi, Naoko Inoue
  • Publication number: 20150043867
    Abstract: A method for manufacturing a semiconductor optical device includes the steps of growing a stacked layer including lower and upper core layers, a first upper region including a non-doped layer, a second upper region including a p-type layer, and a cap layer; forming an upper mesa by etching the stacked layer; selectively etching the cap layer in the upper mesa on the first and second regions; forming a mask on the upper mesa in the second and third regions; and etching the upper mesa using the mask so as to form first to fourth mesa portions. The first and fourth mesa portions are formed by etching the first and second upper regions, and the second upper region and the cap layer, respectively. The second and third mesa portions are formed by etching the first and second upper regions, and the second upper region and the cap layer, respectively.
    Type: Application
    Filed: August 8, 2014
    Publication date: February 12, 2015
    Inventors: Naoya KONO, Hideki YAGI, Takamitsu KITAMURA
  • Publication number: 20150035800
    Abstract: According to an embodiment, an information terminal apparatus includes: a display device equipped with a touch panel; a position detecting section configured to detect a position of a material body in a three-dimensional space opposite to a display surface of the display device; and a command generating section configured to generate a predetermined command for causing predetermined processing to be executed, on the basis of touch position information of a touch position on the touch panel by a touch operation on the touch panel and position-in-space information of the material body in the three-dimensional space detected by the position detecting section after the touch panel is touched or in a state of the touch panel being touched.
    Type: Application
    Filed: March 6, 2014
    Publication date: February 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mineharu Uchiyama, Yasuhiro Shiino, Mayuko Yoshida, Junya Suzuki, Keiichiro Mori, Hiroyuki Oka, Hideki Yagi, Yoshihiro Kato, Ai Matsui
  • Patent number: 8946842
    Abstract: A method for manufacturing an optical waveguide receiver includes the steps of growing first and second stacked semiconductor layer sections, the second stacked semiconductor layer section including a core layer and a cladding layer; forming a first mask including first and second portions; etching the first and second stacked semiconductor layer sections by using the first mask, the first and second stacked semiconductor layer sections covered with the first portion being etched in a mesa structure, the second stacked semiconductor layer section covered with the second portion being etched in a terrace-shaped structure; removing the second portion from the first mask with the first portion left; selectively etching the cladding layer until exposing a surface of the core layer; and sequentially forming a first metal layer, an insulating film, and a second metal layer on the core layer exposed in the step of selectively etching the cladding layer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: February 3, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ryuji Masuyama, Yoshihiro Yoneda, Hideki Yagi, Naoko Inoue
  • Publication number: 20150023627
    Abstract: A method for producing a semiconductor optical device includes the steps of forming first and second optical waveguides; forming a first resin layer on the first and the second optical waveguides; forming an opening in the first resin layer; forming a first electrode in the opening; forming a second resin layer on the first electrode and the first resin layer; forming a groove in the second resin layer on the first electrode; forming a second electrode on the second resin layer, a side surface of the groove, and the top surface of the first electrode; and forming a third electrode on the second electrode. The second and third electrodes have a region in which the second and third electrodes pass over the second optical waveguide, and, in the region, the first and second resin layers are disposed between the second electrode and the second optical waveguide.
    Type: Application
    Filed: July 11, 2014
    Publication date: January 22, 2015
    Inventors: Daisuke KIMURA, Hideki YAGI, Takamitsu KITAMURA
  • Publication number: 20150024527
    Abstract: A method for producing a spot-size convertor includes the steps of preparing a substrate; forming a stacked semiconductor layer including first and second core layers on the substrate; forming a mesa structure by etching the stacked semiconductor layer using a first mask, the mesa structure including a side surface and a bottom portion of the first core layer; forming a protective mask covering the side surface; etching the bottom portion using the protective mask to form a top mesa; and forming a bottom mesa by etching the second core layer using a second mask. The top mesa includes the first core layer and a portion having a mesa width gradually reduced in a first direction of a waveguide axis. The bottom mesa includes the second core layer and a portion having a mesa width gradually reduced in a second direction opposite to the first direction.
    Type: Application
    Filed: July 15, 2014
    Publication date: January 22, 2015
    Inventors: Hideki YAGI, Naoko KONISHI, Takamitsu KITAMURA, Naoya KONO
  • Publication number: 20140342491
    Abstract: A method for manufacturing a waveguide-type semiconductor device includes the steps of forming an epitaxial structure including a waveguide mesa and a device mesa; forming a mask for selective growth on the epitaxial structure; growing a semiconductor region on an end surface of the device mesa by using the mask for selective growth, the semiconductor region including a side portion having a layer shape and a protruding wall portion; forming an ohmic electrode on a top surface of the device mesa; forming a resin layer on the device mesa and the semiconductor region; forming a resin mask having an opening on the ohmic electrode; forming an electric conductor connecting the ohmic electrode to an electrode pad, the electric conductor passing over the protruding wall portion while making contact with a surface of the resin mask; and removing the resin mask after forming the electric conductor.
    Type: Application
    Filed: May 16, 2014
    Publication date: November 20, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Ryuji Masuyama, Yoshihiro Yoneda, Hideki Yagi, Naoko Konishi
  • Publication number: 20140335644
    Abstract: A method for producing a spot size converter includes the steps of forming a first insulator mask on a stacked semiconductor layer; forming first and second terraces, and a waveguide mesa disposed between the first and second terraces by etching the stacked semiconductor layer using the first insulator mask, the first terrace having first to fourth terrace portions, the second terrace having fifth to eighth terrace portions, the waveguide mesa having first to fourth mesa portions; forming a second insulator mask including a first pattern on the first terrace portion, a second pattern on the fifth terrace portion, a third pattern on the third and fourth mesa portions, and a fourth pattern that integrally covers a region extending from the fourth terrace portion to the eighth terrace portion through the fourth mesa portion; and selectively growing a semiconductor layer by using the second insulator mask.
    Type: Application
    Filed: May 1, 2014
    Publication date: November 13, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Naoko INOUE, Hideki YAGI, Ryuji MASUYAMA, Yoshihiro YONEDA
  • Publication number: 20140291717
    Abstract: A method for manufacturing a Mach-Zehnder modulator includes the steps of forming a stacked semiconductor layer, the stacked semiconductor layer including a first conductivity type semiconductor layer, a core layer and a second conductivity type semiconductor layer, forming a waveguide mesa, the waveguide mesa having a first portion, a second portion and a third portion arranged between the first and second portions; forming a buried region on the waveguide mesa; forming an opening in the buried region on the third portion by etching the buried region using a mask; etching the second conductivity type semiconductor layer in the third portion through the buried region as a mask; and removing the buried region after etching the second conductivity type semiconductor layer. In the step of etching the second conductivity type semiconductor layer, the buried region covers a side surface of the third portion of the waveguide mesa.
    Type: Application
    Filed: April 1, 2014
    Publication date: October 2, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Takamitsu KITAMURA, Hideki YAGI
  • Publication number: 20140294335
    Abstract: A method for manufacturing a semiconductor modulator includes the steps of preparing a substrate having a main surface including first and second areas; forming a stacked semiconductor layer on the main surface; forming an optical waveguide mesa by etching the stacked semiconductor layer using a mask, the optical waveguide mesa including an optical modulation portion; applying a resin on a top surface and a side surface of the optical waveguide mesa and on the substrate; forming a first opening in the resin on the second area of the substrate; forming an underlayer structure on the second area of the substrate in contact with the substrate; and forming a pad electrode on the underlayer structure in contact with the underlayer structure through the first opening of the resin. The underlayer structure includes an insulating layer made of a dielectric material.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 2, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hideki YAGI, Takamitsu KITAMURA, Hirohiko KOBAYASHI, Yoshihiro YONEDA
  • Publication number: 20140254998
    Abstract: A semiconductor optical waveguide device includes a substrate having a first area and a second area, and first, second, and semiconductor mesas on the substrate. The first semiconductor mesa includes a cladding layer and a first mesa portion on the second area, the first mesa portion including first and second portions. The second semiconductor mesa includes an intermediate layer, a first core layer, and first and second mesa portions on the first and second area, respectively. The third semiconductor mesa includes a second core layer, and first and second mesa portions having a greater width than that of the second semiconductor mesa. The first portion of the first semiconductor mesa has a substantially the same width as the second mesa portion of the second semiconductor mesa. The first core layer is optically coupled to the second core layer through the intermediate layer disposed between the first and second core layers.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 11, 2014
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Akira FURUYA, Takamitsu KITAMURA, Hideki YAGI, Naoya KONO
  • Publication number: 20140246746
    Abstract: An optical-to-electrical converter unit includes a substrate having front and back surfaces; an optical waveguide unit; and an optical-to-electrical converter. The optical-to-electrical converter includes a light-receiving element optically coupled to the optical waveguide unit; a capacitance element including first and second conductive layers and an insulating layer disposed between the first and second conducive layers; an electrode pad electrically connected to the light-receiving element; a back electrode formed on the back surface of the substrate; and a via electrode extending from the front surface to the back surface of the substrate. The optical waveguide unit, the light-receiving element, the capacitance element, and the electrode pad are formed on the front surface. The first conductive layer of the capacitance element is electrically connected to the light-receiving element and the electrode pad.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 4, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshihiro YONEDA, Ryuji MASUYAMA, Hideki YAGI, Naoko INOUE
  • Patent number: 8811444
    Abstract: A semiconductor integrated device includes a light-emitting portion including a first lower mesa, a first lower buried layer provided on a side surface of the first lower mesa, a first upper mesa provided above the first lower mesa, and a first upper buried layer provided on a side surface of the first upper mesa; and an optical modulator portion including a second lower mesa, a second lower buried layer provided on a side surface of the second lower mesa, a second upper mesa provided above the second lower mesa, and a second upper buried layer provided on a side surface of the second upper mesa. The first and second lower mesas include first and second core layers optically coupled to each other. The first and second lower buried layers are composed of a semi-insulating semiconductor. The first and second upper buried layers are composed of a resin material.
    Type: Grant
    Filed: January 3, 2013
    Date of Patent: August 19, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hideki Yagi
  • Patent number: 8811830
    Abstract: A multi-channel optical waveguide receiver includes an optical input port; an optical branching unit; light-receiving elements having bias electrodes and signal electrodes; optical waveguides being optically coupled between the optical branching unit and the light-receiving elements; capacitors electrically connected between the bias electrodes and a reference potential, the capacitors and the bias electrodes being connected through interconnection patterns; and a signal amplifier including input electrodes. The optical branching unit, the light-receiving elements, the optical waveguides, and the capacitors are formed on a single substrate, the substrate having an edge extending in a first direction. The signal amplifier and the substrate are arranged in a second direction crossing the first direction. The input electrodes and the signal electrodes are arranged along the edge of the substrate.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: August 19, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshihiro Yoneda, Hideki Yagi, Naoko Inoue
  • Patent number: 8731344
    Abstract: A method for manufacturing a semiconductor optical modulator includes forming a p-type semiconductor layer on a main surface of a p-type semiconductor substrate; forming a pair of stripe-shaped masks on the p-type semiconductor layer, the stripe-shaped masks extending in a first direction along the main surface of the p-type semiconductor substrate and being spaced apart from each other; simultaneously forming a hole and a pair of stripe structures extending in the first direction by etching the p-type semiconductor layer through the stripe-shaped masks, the pair of stripe structures defining the hole; after removing the stripe-shaped masks, forming a buried layer in the hole; forming a core layer on the buried layer and the stripe structures; and forming an upper cladding layer on the core layer. The buried layer is made of a semiconductor material with a lower optical absorption loss than that of the p-type semiconductor layer.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: May 20, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hideki Yagi
  • Patent number: D713525
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: September 16, 2014
    Assignee: Nipro Corporation
    Inventors: Takeshi Oguro, Hideki Yagi