Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the page areas within each of the banks in response to a first operation code; and a group of data input/output terminals. A memory unit area within each of the activated page areas is accessed based on the column address. The row controller generates bank activation signals for the plurality of banks in response to multi-bank information data and a supplied bank address that are supplied along with the first command, and generates the row address of each of the plurality of banks in response to the supplied bank address and a supplied row address. The plurality of banks activate the page areas in response to the bank activation signals and the row addresses generated by the row address calculator.

Abstract: Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof.

Abstract: An image memory, image memory system, and memory controller that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The memory device has: a memory cell array that has a plurality of memory unit areas, each of which is selected by addresses; a plurality of input/output terminals; and an input/output unit provided between the memory cell array and the plurality of input/output terminals.

Abstract: A memory control part 12 cyclically assigns time slots to buffer memory parts 21 to 25 respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM 11. A time slot is determined while assuming the worst case where access to the synchronous RAM is the severest. Time slot groups of [(the number of pixels on one horizontal scanning line)/256] in number are generated in an imaginary one horizontal scanning period, where [ ] denotes an integer portion of the number in the parentheses. For a buffer memory 22 whose data volume changes depending on a compression factor, a time slot ending point may be made variable, or a time slot may be generated by interrupt as an exception.

Abstract: A memory control part 12 cyclically assigns time slots to buffer memory parts 21 to 25 respectively and in each time slot, controls access between the corresponding buffer memory part and a synchronous RAM 11. A time slot is determined while assuming the worst case where access to the synchronous RAM is the severest. Time slot groups of [(the number of pixels on one horizontal scanning line)/256] in number are generated in an imaginary one horizontal scanning period, where [ ] denotes an integer portion of the number in the parentheses. For a buffer memory 22 whose data volume changes depending on a compression factor, a time slot ending point may be made variable, or a time slot may be generated by interrupt as an exception.

Abstract: A write operation is performed by using a sequentially-incremented write address upon a first-in first-out memory device, and a read operation is performed by using a sequentially-incremented read address upon the first-in first-out memory device. The write address is cleared by a write reset signal, and the read address is cleared by a read reset signal. A delay circuit is provided to coincide an effective timing of the write reset signal in the memory cell array with that of the read reset signal in the memory cell array.

Abstract: A color image display control apparatus for receiving a composite color picture signal and processing color image data included in the signal. A color picture signal in an analog form included in the composite color picture signal is converted to a digital form by sampling the analog signal at each cycle of a sampling clock, in and analog to digital converter. The digital image data is processed in a digital image processing circuit. Processed digital data is converted to analog data in a digital to analog converter. Information regarding a phase difference between the sampling clock and each horizontal synchronizing signal in the composite color picture signal is obtained. According to the information, a digital image data in a line corresponding to each horizontal synchronizing signal, which was sampled by the sampling clock, is modified so that the influence of the above phase difference on a displayed image of the processed image data is corrected.

Abstract: In an apparatus for detecting a phase difference between two digital signals including an n stage delay circuit, an n bit register connected to the n stage delay circuit, a signal encoding means connected to the n bit register, and a compensation circuit connected to the encoder, a test signal is applied to the delay circuit first and two different delayed data are obtained by applying a reference signal to the n bit register twice, the delay characteristics of the delay circuit is calculated by using two different data and the period time of the two reference signals, then a signal to be subjected to phase difference detection is applied to the delay circuit to obtain delayed data by applying a reference signal to the n bit register, the delayed data is compensated at the compensating circuit by using the delay characteristics of the delay circuit. Thus, an accurate phase difference between two digital signals is obtained.