Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A direct memory access (DMA) controller is adaptable to control a DMA which is independently made in a plurality of channels of a data processing apparatus, where the plurality of channels have predetermined priority sequences and the DMA controller includes a bus and terminal controller coupled to a system bus for obtaining a right to use the system bus responsive to a transfer request, an interrupt and slave controller coupled to the system bus for controlling an interrupt which is made to a central processing unit (CPU) when a data transfer ends for each of the plurality of channels and for controlling an access from the CPU, and an operation determination part for determining an operation of the DMA controller depending on the transfer request, whether or not the bus and terminal controller obtained the right to use the system bus and whether or not the access is made from the CPU.

Abstract: A semiconductor integrated circuit device includes an internal logic circuit for carrying out a logic operation and generating an output signal based on the logic operation, and an output buffer circuit connected to the internal logic circuit, for outputting the output signal through an output terminal in synchronism with a clock signal. The semiconductor integrated circuit also includes a non-overlap clock generator, and a third-clock generator. The non-overlap clock generator generates a first internal clock signal which falls in synchronism with a falling edge of an external clock signal, and generates a second internal clock signal which falls in synchronism with a rising edge of the external clock signal, the internal logic circuit carrying out the logic operation in synchronism with the first and second internal clock signals.

Abstract: An integrated circuit receiving an input signal and producing output signal including: a set/reset circuit, operatively connected to an internal main circuit, being set in response to the first signal and reset in response to the second signal in a normal mode; an output buffer circuit, connected to the set/reset circuit, for producing the output signal in response to an output of the set/reset circuit; and a control circuit, connected between the internal main circuit and the set/reset circuit, receiving the first signal, a reset signal for initializing the internal main circuit, the first signal, the second signal, and a first test signal, during a DC test mode, the control circuit resetting the set/reset circuit in response to a receipt of the reset signal regardless of the second signal and setting the set/reset circuit in response to a receipt of the first test signal regardless of the reset signal and the first signal.