Patents by Inventor Hidenori Kosugi

Hidenori Kosugi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200074342
    Abstract: A question answering system for presenting an answer to an input question includes: a user input processing unit configured to receive the input question; a machine learning platform configured to generate question information for searching corresponding to the received input question by using a learned model for inferring question information from an input question; a word vector platform and an annotated question search platform configured to generate question information for searching corresponding to the received input question without using the learned model; an answer search processing unit configured to search for an answer corresponding to the question information by using the question information generated by at least one of the machine learning platform and the word vector platform/the annotated question search platform; and a dialog output processing unit configured to present the answer obtained through the searching.
    Type: Application
    Filed: May 24, 2019
    Publication date: March 5, 2020
    Applicant: HITACHI, LTD.
    Inventors: Shunta KARASAWA, Mamoru SUEFUJI, Hidenori KOSUGI
  • Publication number: 20140377578
    Abstract: A welded portion (1) formed at a joint between a plurality of steel plates (10) is formed of a plurality of nuggets (11) arranged along a virtual closed curve (12), and when the thickness of the thinnest steel plate (10) of the steel plates (10) is denoted by t, the diameter d of each nugget (11) is 3 ?t or less, and the pitch p between adjacent nuggets is 2 d or more but no more than 5 d, and the number of nuggets is three or more.
    Type: Application
    Filed: December 19, 2012
    Publication date: December 25, 2014
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Kohei Hisada, Shuhei Ogura, Atsushi Kawakita, Tamotsu Ikeda, Hidenori Kosugi
  • Patent number: 5867664
    Abstract: In a parallel processor system, a plurality of nodes each comprising a processor and a main storage unit are interconnected through a network, wherein a user process is executed under the control of an operating system in each of the nodes and inter-process communications are performed through the network for transmitting and receiving messages among the nodes. Reception buffers are provided in a main storage unit and addressed by pool pages, which are discontinuous in a logical address domain or in a real address domain, in a virtual space used by the user process executed by each node. Additionally, reception buffer control information is located on the main storage unit for managing the reception buffers. A node, when receiving a message, uses communication information included in the received message and reception buffer control information to calculate a real address in the reception buffers for storing the received message.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: February 2, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hidenori Kosugi, Patrick Hamilton
  • Patent number: 5584004
    Abstract: A data processing system is provided which includes a plurality of subsystems each including at least one instruction processor, at least one input/output device and at least one main storage device connected by local bus. The subsystems are connected to one another through bus extenders and inter-subsystem transfer lines. Each of the main storage devices is assigned for a partial address space as a part of the system address space. When an instruction processor or an input/output processor on each of the subsystems makes access to a main storage device, the operation of the system is as follows. If the address of access is in the address space limit of a main storage device on an inner subsystem, access to the main storage device on the inner subsystem is made.
    Type: Grant
    Filed: March 20, 1992
    Date of Patent: December 10, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Aimoto, Akira Ishiyama, Hidenori Kosugi, Masabumi Shibata