Patents by Inventor Hideo Kotani

Hideo Kotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5250468
    Abstract: The method of forming an interlayer insulating film insulating first and second layers of conductor patterns in a semiconductor device includes the steps of preparing a reaction gas including at least ozone and silicon alkoxide, wherein the ratio of ozone with respect to silicon alkoxide is adjusted to be not less than 5 within the reaction gas, and forming an insulating film by CVD reacting the reaction gas at atmospheric pressure at the temperature of 350.degree. C.- 450.degree. C., whereupon the interlayer insulating film includes at least the insulating film formed by atmospheric pressure CVD reaction.
    Type: Grant
    Filed: March 25, 1992
    Date of Patent: October 5, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masazumi Matsuura, Hideo Kotani, Atsuhiro Fujii, Shigeo Nagao, Hideki Genjo
  • Patent number: 5132774
    Abstract: The method of forming an interlayer insulating film insulating first and second layers of conductor patterns in a semiconductor device includes the steps of preparing a reaction gas including at least ozone and silicon alkoxide, wherein the ratio of ozone with respect to silicon alkoxide is adjusted to be not less than 5 within the reaction gas, and forming an insulating film by CVD reacting the reaction gas at atmospheric pressure at the temperature of 350.degree. C.-450.degree. C., whereupon the interlayer insulating film includes at least the insulating film formed by atmospheric pressure CVD reaction.
    Type: Grant
    Filed: November 28, 1990
    Date of Patent: July 21, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masazumi Matsuura, Hideo Kotani, Atsuhiro Fujii, Shigeo Nagao, Hideki Genjo
  • Patent number: 4977105
    Abstract: Conductive layers (5a, 8a) included in a multi-layer structure (30a) are electrically interconnected through an conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) existing under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).
    Type: Grant
    Filed: August 9, 1989
    Date of Patent: December 11, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuo Okamoto, Hideo Kotani, Takio Oono, Kiyoto Watabe, Yasushi Kinoshita, Yoshikazu Nishikawa
  • Patent number: 4872050
    Abstract: Conductive layers (5a, 9a) included in a multi-layer structure (30a) are electrically interconnected through a conductive connection wall (13a) provided in a contact hole (12) and contacting the side surface (22) of the multi-layer structure (30a). The upper conductive layer (11a) existing on the multi-layer structure (30a) and the lower conductive layer (3) exisitng under the multi-layer structure (30a) are electrically interconnected through a conductive film (11b) provided in the contact hole (12). These two interconnections are insulated from each other by an insulating film (18) provided on the connection wall (13a).
    Type: Grant
    Filed: March 15, 1988
    Date of Patent: October 3, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Tatsuo Okamoto, Hideo Kotani, Takio Oono, Kiyoto Watabe, Yasushi Kinoshita, Yoshikazu Nishikawa
  • Patent number: 4411929
    Abstract: A method for manufacturing a semiconductor integrated circuit device having contact apertures with finely-controlled dimensions of 1 .mu.m or less. An ion bombardment layer is formed by bombarding predetermined portions of the substrate of the semiconductor device with nitrogen ions using a direct ion beam imaging technique. The ion bombardment layer is converted into an oxidation-resistant layer by annealing, and an insulating oxide layer is formed on the surface of the substrate in regions other than those on which the oxidation-resistant layer is formed by oxidation. Thereafter, contact recesses are formed upon removing the oxidation-resistant layer.
    Type: Grant
    Filed: August 18, 1981
    Date of Patent: October 25, 1983
    Assignee: Mitsubishi Denki Kabushiki Kaisha LSI Development Laboratory
    Inventors: Shinichi Sato, Hiroshi Harada, Takaaki Fukumoto, Hirozo Takano, Hideo Kotani, Shinpei Kayano