Patents by Inventor Hideo Kurihara
Hideo Kurihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130123388Abstract: Provided are a fiber-reinforced thermoplastic resin composition excellent in terms of dispersion property, moldability, rigidity, and reinforcing property and a process for producing the resin composition. This fiber-reinforced thermoplastic resin composition comprises (a) a polyolefin, (b) a rubbery polymer, (c) spherical silica having a water content of 1,000 ppm or less, (d) ultrafine fibers of a thermoplastic polymer having amide groups in the main chain, and (e) a silane coupling agent, wherein the ingredient (d) has been dispersed as ultrafine fibers having an average diameter of 1 [mu]m or less in a matrix comprising the ingredients (a), (b), and (c), and the ingredients (a), (b), (c), and (d) have been chemically bonded through the ingredient (e).Type: ApplicationFiled: July 13, 2011Publication date: May 16, 2013Applicant: Daimaru Sangyo Co., Ltd.Inventors: Hideo Kurihara, Masashi Yamaguchi, Noriaki Tsukuda
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Publication number: 20060249771Abstract: A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon semiconductor substrate, and impurity diffusion layers are formed on the bottom surfaces of the grooves. A gate insulating film is then formed on the p-type silicon semiconductor substrate. This gate insulating film has a three-layer structure in which a first insulating film made of a silicon oxide film, a charge capturing film made of a silicon nitride film, and a second insulating film made of a silicon oxide film, are laminated in this order. A gate electrode is then formed on the gate insulating film. A convexity formed by the grooves serves as the channel region of the non-volatile semiconductor memory. Even if the device size is reduced, an effective channel length can be secured in this non-volatile semiconductor memory. Thus, excellent stability and reliability can be achieved.Type: ApplicationFiled: July 5, 2006Publication date: November 9, 2006Applicant: FUJITSU LIMITEDInventors: Satoshi Shinozaki, Mitsuteru Iijima, Hideo Kurihara
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Patent number: 7026687Abstract: A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon semiconductor substrate, and impurity diffusion layers are formed on the bottom surfaces of the grooves. A gate insulating film is then formed on the p-type silicon semiconductor substrate. This gate insulating film has a three-layer structure in which a first insulating film made of a silicon oxide film, a charge capturing film made of a silicon nitride film, and a second insulating film made of a silicon oxide film, are laminated in this order. A gate electrode is then formed on the gate insulating film. A convexity formed by the grooves serves as the channel region of the non-volatile semiconductor memory. Even if the device size is reduced, an effective channel length can be secured in this non-volatile semiconductor memory. Thus, excellent stability and reliability can be achieved.Type: GrantFiled: March 14, 2003Date of Patent: April 11, 2006Assignee: Fujitsu LimitedInventors: Satoshi Shinozaki, Mitsuteru Iijima, Hideo Kurihara
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Publication number: 20050161730Abstract: A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon semiconductor substrate, and impurity diffusion layers are formed on the bottom surfaces of the grooves. A gate insulating film is then formed on the p-type silicon semiconductor substrate. This gate insulating film has a three-layer structure in which a first insulating film made of a silicon oxide film, a charge capturing film made of a silicon nitride film, and a second insulating film made of a silicon oxide film, are laminated in this order. A gate electrode is then formed on the gate insulating film. A convexity formed by the grooves serves as the channel region of the non-volatile semiconductor memory. Even if the device size is reduced, an effective channel length can be secured in this non-volatile semiconductor memory. Thus, excellent stability and reliability can be achieved.Type: ApplicationFiled: March 16, 2005Publication date: July 28, 2005Applicant: FUJITSU LIMITEDInventors: Satoshi Shinozaki, Mitsuteru Iijima, Hideo Kurihara
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Patent number: 6750520Abstract: A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.Type: GrantFiled: March 1, 2002Date of Patent: June 15, 2004Assignee: Fujitsu LimitedInventors: Hideo Kurihara, Mitsuteru Iijima, Kiyoshi Itano, Tetsuya Chida
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Publication number: 20030197221Abstract: A proposed non-volatile semiconductor memory and a method of manufacturing the same are directed to performing stable and highly reliable operations. First, grooves are formed in a p-type silicon semiconductor substrate, and impurity diffusion layers are formed on the bottom surfaces of the grooves. A gate insulating film is then formed on the p-type silicon semiconductor substrate. This gate insulating film has a three-layer structure in which a first insulating film made of a silicon oxide film, a charge capturing film made of a silicon nitride film, and a second insulating film made of a silicon oxide film, are laminated in this order. A gate electrode is then formed on the gate insulating film. A convexity formed by the grooves serves as the channel region of the non-volatile semiconductor memory. Even if the device size is reduced, an effective channel length can be secured in this non-volatile semiconductor memory. Thus, excellent stability and reliability can be achieved.Type: ApplicationFiled: March 14, 2003Publication date: October 23, 2003Applicant: Fujitsu LimitedInventors: Satoshi Shinozaki, Mitsuteru Iijima, Hideo Kurihara
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Publication number: 20030143426Abstract: Disclosed is a forgery prevention sheet comprising a multi-layered sheet having at least two layers, wherein there are first and second print patterns at different positions in thickness of the sheet, the first print pattern being formed with a first ink including a first fluorescer and the second print pattern which is different from the first print pattern being formed with a second ink including a second fluorescer.Type: ApplicationFiled: September 26, 2002Publication date: July 31, 2003Inventors: Akira Haneda, Hideo Kurihara
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Patent number: 6579769Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed belowType: GrantFiled: December 1, 2000Date of Patent: June 17, 2003Assignees: Fujitsu Ltd., Advanced Micro Devices, Inc., Fujitsu AMD Semiconductor Ltd.Inventors: Hiroyuki Shimada, Masaaki Higashitani, Hideo Kurihara, Hideki Komori, Satoshi Takahashi
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Publication number: 20020084484Abstract: A nonvolatile semiconductor memory comprises a pair of diffused layers formed in the surface area of a p-type silicon substrate, and a gate electrode (polysilicon film and tungsten silicide film formed on a gate oxide between the diffused layers over the p-type silicon substrate. Silicon nitride film is formed at both ends of the gate oxide so that the carrier trap characteristic may become high locally in areas near the pair of diffused layer. This configuration prevents carrier injection to other than the ends of the gate oxide, ensures reliable recording and storage, and increases reliability by preventing write and erase error.Type: ApplicationFiled: March 1, 2002Publication date: July 4, 2002Applicant: FUJITSU LIMITEDInventors: Hideo Kurihara, Mitsuteru Iijima, Kiyoshi Itano, Tetsuya Chida
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Publication number: 20010005543Abstract: Disclosed is a forgery prevention sheet comprising at least triple-layered construction including a base (2) and outer layers (1) and (3) formed on both side of said base. The outer layers have opacity of 20-92%, preferably of 40-92%. The inner surface of at least one (1) of the outer layers is printed with a fluorescent pigment ink into a predetermined design pattern. The printed pattern is not visible under the sunlight, but becomes visibly luminous to human's naked eye, when the sheet is irradiated with ultraviolet rays from the top and from the bottom. The sheet has no fluorescent ink on or near the top surface and, therefore, provides good printability when subjected to post-printing process with any printing system including a lithographic offset printing press, a laser printer and a thermal transfer printer.Type: ApplicationFiled: December 27, 2000Publication date: June 28, 2001Inventors: Akira Haneda, Hideo Kurihara
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Publication number: 20010000247Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming a first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are flown through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are flown through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below the fType: ApplicationFiled: December 1, 2000Publication date: April 12, 2001Applicant: FUJITSU LIMITED, ADVANCED MICRO DEVICES, INC.Inventors: Hiroyuki Shimada, Masaaki Higashitani, Hideo Kurihara, Hideki Komori, Satoshi Takahashi
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Patent number: 6187640Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below tType: GrantFiled: November 17, 1998Date of Patent: February 13, 2001Assignees: Fujitsu Limited, Advanced Micro Devices, Inc., Fujitsu Amd Semiconductor LimitedInventors: Hiroyuki Shimada, Masaaki Higashitani, Hideo Kurihara, Hideki Komori, Satoshi Takahashi
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Patent number: 5999448Abstract: There is provided a nonvolatile semiconductor memory device which has a floating gate electrode and writes data by injecting electrons into the floating gate electrode by applying a voltage to a control gate electrode and erases the data by extracting the electrons from the floating gate electrode. The nonvolatile semiconductor memory device which includes a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, and a plurality of memory elements each of which is connected to a word line and a bit line at a location where the word line and the bit line are intersected with each other, comprises at least one monitor bit line which intersects with the word lines, and a plurality of monitor elements which are connected to the monitor bit line and the plurality of word lines at locations where the monitor bit line and the plurality of word lines are intersected with each other.Type: GrantFiled: December 30, 1998Date of Patent: December 7, 1999Assignee: Fujitsu LimitedInventors: Hideo Kurihara, Satoshi Takahashi
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Patent number: 5950086Abstract: A semiconductor device is fabricated by the step of forming a first device isolation film in a peripheral circuit region by the use of a first pattern and a second device isolation film in a memory cell region by the use of a second pattern; forming a first conducting film processed by the use of a third pattern having a pattern-to-be-removed in a peripheral edge of the memory cell region; the step of forming an insulation film covering the memory cell region and processed by the use of a fourth pattern whose peripheral edge is positioned on the pattern-to-be-removed of the third pattern; and the step of forming a second conducting film processed by a fifth pattern.Type: GrantFiled: June 18, 1997Date of Patent: September 7, 1999Assignee: Fujitsu LimitedInventors: Satoshi Takahashi, Tatsuya Kajita, Hideo Kurihara, Hideki Komori, Masaaki Higashitani
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Patent number: 5948503Abstract: A fine fiber-reinforced elastomer composition (A) having a high elastic modulus, mechanical strength and creep resistance includes (a) 100 parts by weight of elastic component having a glass-transition temperature of 0.degree. C. or less, (b) 30 to 500 parts by weight of a polyolefin component and (c) 10 to 500 parts by weight of a polyamide component dispersed in the fine fiber form in the matrix consisting of the components (a) and (b), these components (a), (b) and (c) being chemically bonded to each other through a binding agent (d), for example, a silane coupling agent, and is useful for producing an elastic material having a high elastic modulus, an excellent fatigue resistance and a high isotropy, by admixing an additional elastic component (B) to the elastomer composition (A).Type: GrantFiled: August 30, 1995Date of Patent: September 7, 1999Assignee: UBE Industries, Ltd.Inventors: Shinji Yamamoto, Kazuyoshi Fujii, Hideo Kurihara, Tatsuo Wada
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Patent number: 5606159Abstract: An information recording medium cleaning device includes moving the recording medium and the cleaning device relative to each other and a detection device for detecting a degree of stain caused by dust, fingerprints or oil, for example, on the information recording medium. Cleaning is performed based on the degree of stain detected on the information recording medium.Type: GrantFiled: June 7, 1995Date of Patent: February 25, 1997Assignee: Canon Kabushiki KaishaInventor: Hideo Kurihara
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Patent number: 5428213Abstract: An information recording medium cleaning device includes moving the recording medium and the cleaning device relative to each other and a detection device for detecting a degree of stain caused by dust, fingerprints or oil, for example, on the information recording medium. Cleaning is performed based on the degree of stain detected on the information recording medium.Type: GrantFiled: November 12, 1993Date of Patent: June 27, 1995Assignee: Canon Kabushiki KaishaInventor: Hideo Kurihara
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Patent number: 5150352Abstract: An information recording and reproducing apparatus according to the invention includes an emergency conveying device for conveying an information recording medium on a carriage member from an information recording and/or reproducing position to an ejecting port. The emergency conveying device includes a device for moving the carriage member to the ejecting port by coming into engagement with the carriage member. A gear (20) is manually actuated in case of a power failure so as to manually move the carriage (3) toward the discharge area.Type: GrantFiled: September 26, 1989Date of Patent: September 22, 1992Assignee: Canon Kabushiki KaishaInventor: Hideo Kurihara
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Patent number: 5049610Abstract: A reinforced rubber composition comprising 100 parts by weight of a vulcanizable rubber including 1 to 100 parts by weight of fine short fibers of a fiber forming polyamide buried therein, and the polyamide and the rubber are bonded through a silane coupling agent. This reinforced rubber composition is suitable for use as automobile tires and the parts thereof and rubber products such as, rubber houses, rubber belts, rubber parts for automobiles, and footwear materials.Type: GrantFiled: November 17, 1989Date of Patent: September 17, 1991Assignee: Ube Industries, Ltd.Inventors: Takeshi Takaki, Kouhei Kaijiri, Denichi Oda, Kunio Oda, Hideo Kurihara, Takeshi Tanabe
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Patent number: 5006603Abstract: A reinforced rubber composition comprising 100 parts by weight of a vulcanizable rubber including 1 to 100 parts by weight of fine short fibers of a fiber forming polyamide buried therein, and the polyamide and the rubber are bonded through a silane coupling agent. This reinforced rubber composition is suitable for use as automobile tires and the parts thereof and rubber products such as, rubber houses, rubber belts, rubber parts for automobiles, and footwear materials.Type: GrantFiled: September 16, 1987Date of Patent: April 9, 1991Assignee: Ube Industries, Ltd.Inventors: Takeshi Takaki, Kouhei Kaijiri, Denichi Oda, Kunio Oda, Hideo Kurihara, Takeshi Tanabe