Patents by Inventor Hideo Ohno

Hideo Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240071452
    Abstract: The present invention provides an access controller, and a data transfer method. The access controller controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 29, 2024
    Applicant: TOHOKU UNIVERSITY
    Inventors: Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Takahiro Hanyu, Tetsuo Endoh, Hideo Ohno
  • Patent number: 11862217
    Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.
    Type: Grant
    Filed: February 15, 2020
    Date of Patent: January 2, 2024
    Assignee: TOHOKU UNIVERSITY
    Inventors: Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Takahiro Hanyu, Tetsuo Endoh, Hideo Ohno
  • Patent number: 11690299
    Abstract: Provided is an X-type 3-terminal STT-MRAM (spin orbital torque magnetization reversal component) having a high thermal stability index ? and a low writing current IC in a balanced manner. A magnetoresistance effect element has a configuration of channel layer (1)/barrier layer non adjacent magnetic layer (2b)/barrier layer adjacent magnetic layer (2a)/barrier layer (3).
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: June 27, 2023
    Assignee: Tohoku University
    Inventors: Hideo Sato, Shinya Ishikawa, Shunsuke Fukami, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11600313
    Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: March 7, 2023
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11563169
    Abstract: A magnetic tunnel junction element (10) includes a configuration in which a reference layer (14) that includes a ferromagnetic material, a barrier layer (15) that includes O, a recording layer (16) that includes a ferromagnetic material including Co or Fe, a first protective layer (17) that includes O, and a second protective layer (18) that includes at least one of Pt, Ru, Co, Fe, CoB, FeB, or CoFeB are layered.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 24, 2023
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hideo Sato, Yoshihisa Horikawa, Shunsuke Fukami, Shoji Ikeda, Fumihiro Matsukura, Hideo Ohno, Tetsuo Endoh, Hiroaki Honjo
  • Patent number: 11557719
    Abstract: There is provided a magnetoresistance effect element includes: a channel layer that extends in a first direction; a recording layer which includes a film formed from a ferromagnetic material, of which a magnetization state is changed to one of two or greater magnetization states, and which is formed on the channel layer; a non-magnetic layer that is provided on a surface of the recording layer; a reference layer which is provided on a surface of the non-magnetic layer, which includes a film formed from a ferromagnetic material, and of which a magnetization direction is fixed; a terminal pair that includes a first terminal and a second terminal which are electrically connected to the channel layer with an interval in the first direction, and to which a current pulse for bringing the recording layer to any one magnetization state with a plurality of pulses is input by flowing a current to the channel layer between the first terminal and the second terminal; and a third terminal that is electrically connected to
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: January 17, 2023
    Assignee: TOHOKU UNIVERSITY
    Inventors: Shunsuke Fukami, Aleksandr Kurenkov, William Andrew Borders, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20220350572
    Abstract: A random number generation unit and a computing system using the same, the unit including a magnetic tunnel junction element and being capable of developing the characteristics required for the execution of probabilistic computing and operating at a higher speed. A magnetic tunnel junction element includes a fixed layer having a ferromagnet and having a magnetization direction fixed substantially, a free layer having a ferromagnet and having a magnetization direction varying with a first time constant, and a barrier layer disposed between the layers configured with an insulator. The magnetic tunnel junction element has a shift magnetic field of an absolute value of 20 millitesla or smaller. The fixed layer has a plurality of ferromagnetic and non-magnetic coupling layers laminated one upon another, and ferromagnetic layers adjacent to each other among the respective ferromagnetic layers are coupled in terms of magnetization by the non-magnetic coupling layers in an antiparallel manner.
    Type: Application
    Filed: May 25, 2020
    Publication date: November 3, 2022
    Applicant: TOHOKU UNIVERSITY
    Inventors: Shunsuke FUKAMI, William Andrew BORDERS, Takuya FUNATSU, Shun KANAI, Keisuke HAYAKAWA, Hideo OHNO
  • Patent number: 11462253
    Abstract: Provided is a magnetoresistance effect element in which the magnetization direction of the recording layer is perpendicular to the film surface and which has a high thermal stability factor ?, and a magnetic memory. A recording layer having a configuration of first magnetic layer/first non-magnetic coupling layer/first magnetic insertion layer/second non-magnetic coupling layer/second magnetic layer is sandwiched between the first and second non-magnetic layers and stacked so that a magnetic coupling force is generated between the first magnetic layer and the second magnetic layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: October 4, 2022
    Assignee: TOHOKU UNIVERSITY
    Inventors: Koichi Nishioka, Tetsuo Endoh, Shoji Ikeda, Hiroaki Honjo, Hideo Sato, Hideo Ohno
  • Publication number: 20220157361
    Abstract: The present invention provides a device with low power and high performance, which can be applied to sensor nodes, a sensor node using the same, an access controller, a data transfer method, and execute a processing method in a microcontroller. The device has: an MRAM; a non-volatile CPU configured to include a nonvolatile memory; a non-volatile FPGA-ACC configured to include a nonvolatile memory and execute a part of operations on the nonvolatile CPU; and a power-gating control unit that controls power supply to each memory cell in the MRAM, the non-volatile CPU, and the non-volatile FPGA-ACC. The device is further provided with an access controller that controls accesses to the MRAM by reading data in advance and backing up the data when data is to be read from the MRAM.
    Type: Application
    Filed: February 15, 2020
    Publication date: May 19, 2022
    Applicant: TOHOKU UNIVERSITY
    Inventors: Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Takahiro Hanyu, Tetsuo Endoh, Hideo Ohno
  • Publication number: 20220059149
    Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element, a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on the cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.
    Type: Application
    Filed: November 3, 2021
    Publication date: February 24, 2022
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11200933
    Abstract: The magnetic memory element (100) includes: a conductive layer that includes a heavy metal layer (10) containing a 5d transition metal; a first ferromagnetic layer (20) that is adjacent to the conductive layer and contains a ferromagnetic layer having a reversible magnetization; a barrier layer (30) that is adjacent to the first ferromagnetic layer (20) and includes an insulating material; a reference layer (40) that is adjacent to the barrier layer (30) and has at least one second ferromagnetic layer (41) having a fixed magnetization direction; a cap layer (50) that is adjacent to the reference layer (40) and includes a conductive material; a first terminal (T1) that is capable of introducing a current into one end of the heavy metal layer (10) in the longitudinal direction; a second terminal (T2) that is capable of introducing a current into the other end of the heavy metal layer (10) in the longitudinal direction; and a third terminal (T3) that is capable of introducing a current into the cap layer (50).
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: December 14, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Shunsuke Fukami, Chaoliang Zhang, Ayato Ohkawara, Kyota Watanabe, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11183228
    Abstract: A memory circuit device includes multiple memory cells that are each constituted of a resistive memory element; a write circuit unit that is configured to write data to any one of the memory cells which is designated by cell designating information, and a read circuit unit that is configured to read out, from the memory cell designated by the cell designating information, data written in the memory cell. The memory circuit device has a configuration including a selection circuit unit that is shared by both of the write circuit unit and the read circuit unit and configured to select a memory cell to be activated from the multiple memory cells based on cell designating information, and a control circuit unit that is configured to selectively enable any one of writing of data by the write circuit unit and reading of data by the read circuit unit with respect to the memory cell selected by the selection circuit unit.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: November 23, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11133046
    Abstract: A data write device for a resistive memory element, the resistive memory element including: a conductive electrode provided at one end of the memory element; and a reading electrode provided at the other end of the memory element being configured to vary a resistance of the memory element by applying a write current to the conductive electrode, the data write device for the resistive memory element further includes: a writing means, an output means, and a control means. The output means is provided between a power supply and the reading electrode. As output signals, a read signal from the memory element and a monitor signal to monitor a writing status of the memory element written by the writing means are output from the output means. By the monitor signal, a termination of data-writing into the resistive memory element is detected.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: September 28, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh
  • Patent number: 11121310
    Abstract: A structure used in the formation of a spintronics element, the spintronics element to include a plurality of laminated layers, includes a substrate, a plurality of laminated layers formed on the substrate, an uppermost layer of the plurality of laminated layers being a non-magnetic layer containing oxygen, and a protection layer directly formed on the uppermost layer, the protection layer preventing alteration of characteristics of the uppermost layer while exposed in an atmosphere including H2O, a partial pressure of H2O in the atmosphere being equal to or larger than 10?4 Pa, no other layer being directly formed on the protection layer.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: September 14, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Soshi Sato, Masaaki Niwa, Hiroaki Honjo, Shoji Ikeda, Hideo Ohno, Tetsuo Endo
  • Patent number: 11081641
    Abstract: The present invention provides a magnetoresistance effect element which has a high thermal stability factor ? and in which a magnetization direction of a recording layer is a perpendicular direction with respect to a film surface, and a magnetic memory including the same. Magnetic layers of a recording layer of the magnetoresistance effect element are divided into at least two, and an Fe composition with respect to a sum total of atomic fractions of magnetic elements in each magnetic layer is changed before stacking the magnetic layers.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: August 3, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjo, Tetsuo Endoh, Shoji Ikeda, Hideo Sato, Hideo Ohno
  • Patent number: 11054463
    Abstract: A method and a system for measuring the thermal stability factor of a magnetic tunnel junction device, a semiconductor integrated circuit, and a production management method for the semiconductor integrated circuit, capable of measuring the thermal stability factors of individual devices in a relatively short period of time and quickly performing quality control during material development and at a production site. A meter measures change in resistance value of an evaluation MTJ for a predetermined period while causing a predetermined current to flow into the evaluation MTJ maintained at a predetermined temperature. An analyzer calculates a time constant in which a low-resistance state is maintained and a time constant in which a high-resistance state is maintained from the measured change in resistance value. A thermal stability factor of the evaluation MTJ is calculated on the basis of the calculated time constants and the predetermined current flowing into the evaluation MTJ.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: July 6, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kenchi Ito, Tetsuo Endoh, Hideo Sato, Takashi Saito, Masakazu Muraguchi, Hideo Ohno
  • Patent number: 10998491
    Abstract: A magnetoresistance effect element is provided, which can, even in a region where the element size of the magnetoresistance effect element is small, implement stable record holding at higher temperatures, and moreover which has higher thermal stability. The magnetoresistance effect element has a configuration including reference layer (B1)/first non-magnetic layer (1)/first magnetic layer (21)/first non-magnetic insertion layer (31)/second magnetic layer (22). A magnetostatic coupling is established between the first magnetic layer (21) and the second magnetic layer (22) due to magnetostatic interaction becoming dominant.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: May 4, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kyota Watanabe, Shunsuke Fukami, Hideo Sato, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20210119114
    Abstract: There is provided a magnetoresistance effect element includes: a channel layer that extends in a first direction; a recording layer which includes a film formed from a ferromagnetic material, of which a magnetization state is changed to one of two or greater magnetization states, and which is formed on the channel layer; a non-magnetic layer that is provided on a surface of the recording layer; a reference layer which is provided on a surface of the non-magnetic layer, which includes a film formed from a ferromagnetic material, and of which a magnetization direction is fixed; a terminal pair that includes a first terminal and a second terminal which are electrically connected to the channel layer with an interval in the first direction, and to which a current pulse for bringing the recording layer to any one magnetization state with a plurality of pulses is input by flowing a current to the channel layer between the first terminal and the second terminal; and a third terminal that is electrically connected to
    Type: Application
    Filed: January 30, 2019
    Publication date: April 22, 2021
    Inventors: Shunsuke Fukami, Aleksandr Kurenkov, William Andrew Borders, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20210098689
    Abstract: A magnetoresistance effect element is provided, which can, even in a region where the element size of the magnetoresistance effect element is small, implement stable record holding at higher temperatures, and moreover which has higher thermal stability. The magnetoresistance effect element has a configuration including reference layer (B1)/first non-magnetic layer (1)/first magnetic layer (21)/first non magnetic insertion layer (31)/second magnetic layer (22). A magnetostatic coupling is established between the first magnetic layer (21) and the second magnetic layer (22) due to magnetostatic interaction becoming dominant.
    Type: Application
    Filed: February 6, 2016
    Publication date: April 1, 2021
    Inventors: Kyota WATANABE, Shunsuke FUKAMI, Hideo SATO, Hideo OHNO, Tetsuo ENDOH
  • Patent number: 10896729
    Abstract: A data write circuit of a resistive memory element is provided, the device being capable of writing with low writing energy using a simple circuit. The data write circuit of the resistive memory element, includes: a complementary resistive memory element; writing means for making the complementary resistive memory element cause a resistance change; detection means for detecting a writing state in the complementary resistive memory element; and control means for controlling writing by the writing means, based on a detected signal of the detection means.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 19, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Takahiro Hanyu, Daisuke Suzuki, Hideo Ohno, Tetsuo Endoh