Patents by Inventor Hideomi Suzawa

Hideomi Suzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210408298
    Abstract: A semiconductor device with high reliability is provided. A first conductor and a second conductor are provided over and in contact with a first oxide. A first insulator is provided to cover the first oxide, a first conductor, and a second conductor. The first insulator includes an opening portion. The first oxide is exposed on a bottom surface of the opening portion. A side surface of the first conductor and a side surface of the second conductor are exposed on a side surface of the opening portion. A second oxide is provided in contact with the first oxide, the side surface of the first conductor, and the second conductor in the opening portion. A second insulator is provided in the opening portion with the second oxide therebetween. A third conductor is provided in the opening portion with the second insulator therebetween. Lower end portions of the side surface of the first conductor and the second conductor touch an ellipse or a circle with a center above the first oxide.
    Type: Application
    Filed: November 19, 2019
    Publication date: December 30, 2021
    Inventors: Shunpei YAMAZAKI, Erika TAKAHASHI, Hideomi SUZAWA, Shinya SASAGAWA
  • Publication number: 20210384353
    Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes first and second transistors and first and second capacitors. Each of the first and second transistors includes a gate insulator and a gate electrode over an oxide. Each of the first and second capacitors includes a conductor, a dielectric over the conductor, and the oxide. The first and second transistors are provided between the first capacitor and the second capacitor. One of a source and a drain of the first transistor is also used as one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is also used as one electrode of the first capacitor. The other of the source and the drain of the second transistor is also used as one electrode of the second capacitor. The channel lengths of the first and second transistors are larger than the lengths in a direction parallel to short sides of fourth and fifth conductors.
    Type: Application
    Filed: August 21, 2018
    Publication date: December 9, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuta ENDO, Hideomi SUZAWA
  • Patent number: 11183516
    Abstract: A semiconductor device with reduced parasitic capacitance is provided. The semiconductor device includes a first insulating layer; a first oxide layer over the first insulating layer; a semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer over the semiconductor layer; a second insulating layer over the first insulating layer; a third insulating layer over the second insulating layer, the source electrode layer, and the drain electrode layer; a second oxide layer over the semiconductor layer; a gate insulating layer over the second oxide layer; a gate electrode layer over the gate insulating layer; and a fourth insulating layer over the third insulating layer, the second oxide layer, the gate insulating layer, and the gate electrode layer.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: November 23, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideomi Suzawa, Yuta Endo, Kazuya Hanaoka
  • Publication number: 20210320212
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Tetsuhiro TANAKA, Hirokazu WATANABE, Yuhei SATO, Yasumasa YAMANE, Daisuke MATSUBAYASHI
  • Publication number: 20210305413
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Application
    Filed: February 4, 2021
    Publication date: September 30, 2021
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Shinya SASAGAWA, Motomu KURATA, Masashi TSUBUKU
  • Patent number: 11107929
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, a third insulator over the second insulator, a fourth insulator and a first conductor over the third insulator, a fifth insulator over the fourth insulator and the first conductor, a first oxide over the fifth insulator, a second conductor and a third conductor over the first oxide, a second oxide over the first oxide and between the second conductor and the third conductor, a sixth insulator over the second oxide, and a fourth conductor over the sixth insulator. The hydrogen concentration of the second insulator is lower than that of the first insulator. The hydrogen concentration of the third insulator is lower than that of the second insulator.
    Type: Grant
    Filed: November 21, 2019
    Date of Patent: August 31, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tsutomu Murakawa, Hideomi Suzawa
  • Patent number: 11049974
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 29, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe, Yuhei Sato, Yasumasa Yamane, Daisuke Matsubayashi
  • Publication number: 20210082967
    Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi SUZAWA
  • Patent number: 10944014
    Abstract: To provide a transistor having a high on-state current. A semiconductor device includes a first insulator containing excess oxygen, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor which are over the second oxide semiconductor and are separated from each other, a third oxide semiconductor in contact with side surfaces of the first oxide semiconductor, a top surface and side surfaces of the second oxide semiconductor, a top surface of the first conductor, and a top surface of the second conductor, a second insulator over the third oxide semiconductor, and a third conductor facing a top surface and side surfaces of the second oxide semiconductor with the second insulator and the third oxide semiconductor therebetween. The first oxide semiconductor has a higher oxygen-transmitting property than the third oxide semiconductor.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: March 9, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akihisa Shimomura, Yuhei Sato, Yasumasa Yamane, Yoshitaka Yamamoto, Hideomi Suzawa, Tetsuhiro Tanaka, Yutaka Okazaki, Naoki Okuno, Takahisa Ishiyama
  • Publication number: 20210057586
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Application
    Filed: July 8, 2020
    Publication date: February 25, 2021
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Hideomi SUZAWA
  • Patent number: 10923580
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: February 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Shinya Sasagawa, Motomu Kurata, Masashi Tsubuku
  • Patent number: 10854636
    Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: December 1, 2020
    Inventors: Koji Ono, Hideomi Suzawa
  • Publication number: 20200279851
    Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, and an electrode. The first transistor and the second transistor include an oxide, a gate insulator over the oxide, and a gate. The electrode is connected to one of a source and a drain of the first transistor and one of a source and a drain of the second transistor. The channel length of the first transistor is longer than the short side of the first conductor. The channel length of the second transistor is longer than the short side of the second conductor.
    Type: Application
    Filed: September 5, 2018
    Publication date: September 3, 2020
    Inventors: Yuta ENDO, Hideomi SUZAWA
  • Patent number: 10720532
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: July 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Hideomi Suzawa
  • Publication number: 20200227566
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Tetsuhiro TANAKA, Hirokazu WATANABE, Yuhei SATO, Yasumasa YAMANE, Daisuke MATSUBAYASHI
  • Publication number: 20200203533
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first insulator, a second insulator over the first insulator, a third insulator over the second insulator, a fourth insulator and a first conductor over the third insulator, a fifth insulator over the fourth insulator and the first conductor, a first oxide over the fifth insulator, a second conductor and a third conductor over the first oxide, a second oxide over the first oxide and between the second conductor and the third conductor, a sixth insulator over the second oxide, and a fourth conductor over the sixth insulator. The hydrogen concentration of the second insulator is lower than that of the first insulator. The hydrogen concentration of the third insulator is lower than that of the second insulator.
    Type: Application
    Filed: November 21, 2019
    Publication date: June 25, 2020
    Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Hideomi SUZAWA
  • Patent number: 10672913
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 2, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe, Yuhei Sato, Yasumasa Yamane, Daisuke Matsubayashi
  • Publication number: 20200144425
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Application
    Filed: September 3, 2019
    Publication date: May 7, 2020
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Hideomi SUZAWA
  • Publication number: 20200066884
    Abstract: The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Shinya SASAGAWA, Motomu KURATA, Masashi TSUBUKU
  • Patent number: 10522397
    Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hideomi Suzawa, Sachiaki Tezuka, Tetsuhiro Tanaka, Toshiya Endo, Mitsuhiro Ichijo