Abstract: A contact vibration detection device 100 for detecting contact vibration due to contact between a rotational shaft 12 and a stationary part 13 includes: a rotation waveform determination unit 101 configured to determine a rotation waveform of the rotational shaft 12 based on displacement of the rotational shaft 12 during rotation; a parameter change detection unit 102 configured to detect a change in a parameter of at least one of an effective value of the rotation waveform or a phase angle of the rotation waveform; and a contact vibration determination unit 103 configured to determine whether the contact vibration occurs based on presence or absence of the change in the parameter.

Abstract: A wave power generation system includes: a hydraulic pump device configured to operate by force of a wave to discharge an operating liquid to a main passage; a hydraulic motor device configured to be rotated by the operating liquid flowing through the main passage; a power generator configured to be driven by the hydraulic motor to generate electric power; and a heat exchanger device configured to perform heat exchange of the operating liquid. The heat exchanger device includes a heat exchange motor device connected to the main passage through a sub passage and configured to be operated by the operating liquid introduced through the sub passage, a refrigerant pump device driven by the heat exchange motor device and configured to suck and discharge a refrigerant liquid, and a heat exchanger to which the refrigerant liquid discharged from the heat exchange pump device and the operating liquid are introduced.

Abstract: According to one embodiment, a first string is coupled to the bit line via a first transistor and includes a first cell transistor. A second string is coupled to the bit line via a second transistor and includes a second cell transistor. The first and second cell transistors are coupled to the word line. A controller is configured to instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor. The controller is further configured to instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.

Abstract: According to one embodiment, a first string is coupled to the bit line via a first transistor and includes a first cell transistor. A second string is coupled to the bit line via a second transistor and includes a second cell transistor. The first and second cell transistors are coupled to the word line. A controller is configured to instruct the memory device to write first data to the first cell transistor and to write second data to the second cell transistor. The controller is further configured to instruct the memory device to read data from the first cell transistor while storing the first data and the second data after making the instruction for writing the first data and the second data.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory and a memory controller. The memory controller has a first signal generation section that generates a first signal related with a read voltage used for read operation of the nonvolatile semiconductor memory, a second signal generation section that generates a second signal that specifies the temperature coefficient used for the correction for temperature of the read voltage, and a first interface section that outputs the first signal, the second signal and a read command. The nonvolatile semiconductor memory has a word line, a memory cell array includes memory cells connected to the word line, and a second interface section that receives the first signal, the second signal and the read command.

Abstract: A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a storage area having a plurality of memory cells configured to store data. The control circuit determines whether data write to the storage area is possible or impossible.

Abstract: According to one embodiment, a memory system includes a memory unit, a first controller, and a second controller. In the memory unit, first to fourth levels (first level<second level<third level<fourth level) are written based on first and second data. The first controller comprises a first write mode of writing the fourth level based on the data of the second page and then writing the second and third levels and a second write mode of writing the third and fourth levels and then writing the second level. The second controller issues at least one of second and third commands to be supplied to the first controller in order to select at least one of the first and second write modes.

Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.

Abstract: A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a control circuit. The nonvolatile memory includes a storage area having a plurality of memory cells configured to store data. The control circuit determines whether data write to the storage area is possible or impossible.

Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.

Abstract: According to one embodiment, a memory system includes a memory unit, a first controller, and a second controller. In the memory unit, first to fourth levels (first level<second level<third level<fourth level) are written based on first and second data. The first controller comprises a first write mode of writing the fourth level based on the data of the second page and then writing the second and third levels and a second write mode of writing the third and fourth levels and then writing the second level. The second controller issues at least one of second and third commands to be supplied to the first controller in order to select at least one of the first and second write modes.

Abstract: A memory device includes a memory chip that stores data, and an external controller that controls the memory chip. The memory chip includes multiple memory cells configured to store data of two or more bits; and an internal controller that executes a program operation for page data including a lower and an upper page program operation, and executes a read operation for page data including a lower and an upper page read operation. The external controller includes an error correction unit that performs error correction encoding on data to be programmed into the memory cell array and performs error correction decoding on data. The internal controller outputs the read page data from the memory cell array to the external controller, regardless of whether the upper page program operation is complete or not, in the upper page read operation.

Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.

Abstract: A memory system with a semiconductor memory device, in which a physical block of n-bits serves as an erase unit, wherein the address management of the memory device is performed by a logical block with m-bits, “m” being larger than “n” and expressed by a power of two, and wherein a n-bit portion continued from the head address in the logical block is defined as a first management unit corresponding to one physical block of the memory device, and a number of the remaining fraction portions each defined as a second management unit are gathered so as to correspond to one physical block of the memory device.

Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.

Abstract: A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, data in the first memory block and data in the second memory block being each erased at a time. The arithmetic processing device writes the data to the memory cells in the first memory block using an upper bit and a lower bit of the at least 2 bits and writes the data to the memory cells in the second memory block using only the lower bit of the at least 2 bits.

Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.