Patents by Inventor Hideto Fukuda

Hideto Fukuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9257671
    Abstract: A resin composition for sealing an organic electroluminescent device, containing: a drying agent, and a curable component, wherein a surface roughness Ra of the shear failure surface after curing the resin composition is 0.5 ?m or more; a production method thereof; an adhesive film and a gas-barrier formed of the resin composition; an organic electroluminescent device and an organic electroluminescent panel using the same.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: February 9, 2016
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Toshihiro Suzuki, Satoshi Hattori, Tetsuya Mieda, Hideto Fukuda, Takanori Yamakawa, Toshimitsu Nakamura
  • Publication number: 20140291655
    Abstract: A resin composition for sealing an organic electroluminescent device, containing: a drying agent, and a curable component, wherein a surface roughness Ra of the shear failure surface after curing the resin composition is 0.5 ?m or more; a production method thereof; an adhesive film and a gas-barrier formed of the resin composition; an organic electroluminescent device and an organic electroluminescent panel using the same.
    Type: Application
    Filed: June 12, 2014
    Publication date: October 2, 2014
    Inventors: Toshihiro SUZUKI, Satoshi HATTORI, Tetsuya MIEDA, Hideto FUKUDA, Takanori YAMAKAWA, Toshimitsu NAKAMURA
  • Patent number: 8581623
    Abstract: A lookup table includes a single via layer having 2N via insertion portions corresponding to 2N input patterns provided from N input terminals; and a via inserted into at least one of the via insertion portions, the via connecting the input terminal and an output terminal.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hideto Fukuda
  • Patent number: 8584069
    Abstract: A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: November 12, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kenichi Ushiyama, Shigenori Ichinose, Kenji Suzuki, Kenji Kumagai, Takafumi Miyahara, Shuji Tanahashi, Hideto Fukuda
  • Patent number: 8531207
    Abstract: A lookup table includes a single via layer having 2N via insertion portions corresponding to 2N input patterns provided from N input terminals; and a via inserted into at least one of the via insertion portions, the via connecting the input terminal and an output terminal.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: September 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hideto Fukuda
  • Patent number: 7978168
    Abstract: A D/A converter for receiving a plurality of divisional voltages and converting a digital signal to an analog voltage with the divisional voltages, the D/A converter includes a selection circuit for receiving the divisional voltages and the digital signal to select one of the divisional voltages. The selection circuit includes a plurality of first switch circuits that are selectively activated in response to the digital signal to select one of the divisional voltages, with each of the first switch circuits being provided with a logic switch function and having an ON resistance when activated, and at least an activated one of the first switch circuits further dividing the selected one of the divisional voltages with the ON resistance. The plurality of switch circuits includes at least one voltage dividing switch circuit used to further divide the selected one of the divisional voltages.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: July 12, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
  • Publication number: 20110078646
    Abstract: A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.
    Type: Application
    Filed: September 28, 2010
    Publication date: March 31, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Kenichi Ushiyama, Shigenori Ichinose, Kenji Suzuki, Kenji Kumagai, Takafumi Miyahara, Shuji Tanahashi, Hideto Fukuda
  • Patent number: 7903071
    Abstract: A driver IC for a display that includes a first D/A converter with a 1st selection circuit that receives 1st image signals and supplies a selected positive divisional voltage to a 1st operational amplifier, which supplies a positive pixel voltage by amplifying the selected positive divisional voltage; a 2nd D/A converter with a 2nd selection circuit that receives 2nd image signals and supplies a selected negative divisional voltage to a 2nd operational amplifier, which supplies a negative pixel voltage by amplifying the selected negative divisional voltage; and a polarity switching switch with 1st and 2nd switches connecting the 1st and 2nd D/A converters respectively, the polarity switching switch being switched to supply each of output terminals corresponding to the 1st and 2nd image signals alternately with the positive and negative pixel voltages every horizontal scan period by activating/inactivating the 1st and 2nd switches in a complementary manner.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: March 8, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
  • Publication number: 20100225354
    Abstract: A lookup table includes a single via layer having 2N via insertion portions corresponding to 2N input patterns provided from N input terminals; and a via inserted into at least one of the via insertion portions, the via connecting the input terminal and an output terminal.
    Type: Application
    Filed: February 26, 2010
    Publication date: September 9, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hideto FUKUDA
  • Publication number: 20070296679
    Abstract: A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.
    Type: Application
    Filed: August 6, 2007
    Publication date: December 27, 2007
    Inventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
  • Publication number: 20070296678
    Abstract: A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.
    Type: Application
    Filed: August 6, 2007
    Publication date: December 27, 2007
    Inventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
  • Patent number: 7268763
    Abstract: A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: September 11, 2007
    Assignee: Fujitsu Limited
    Inventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
  • Patent number: 7180512
    Abstract: An integrated circuit includes a first signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input signal, followed by outputting the first input signal after logic inversion thereof in response to a first state of a switching signal and outputting the first input signal without logic inversion in response to a second state of the switching signal, a signal processing circuit which performs signal processing based on the output of the first signal-inversion switching circuit, and a second signal-inversion switching circuit which receives the output of the first signal-inversion switching circuit passing through the signal processing circuit as a second input signal, followed by outputting the second input signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input signal without logic inversion in response to the first state of the switching signal.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: February 20, 2007
    Assignee: Fujitsu Limited
    Inventors: Masao Kumagai, Hideto Fukuda, Shinya Udo
  • Publication number: 20040090408
    Abstract: A drive circuit of a display that decreases the number of gates in a selection circuit to reduce chip area. The drive circuit includes a first voltage dividing circuit for generating a plurality of divisional voltages by dividing a predetermined reference voltage. A selection circuit receives a selection signal and selects one of the divisional voltages. The selection circuit includes a plurality of first switch circuits selectively activated in response to the selection signal to select one of the divisional voltages. Each of the first switch circuits is provided with a logic switch function and has an ON resistance when activated. An activated one of the first switch circuits generates the pixel voltage by further dividing the selected one of the divisional voltages.
    Type: Application
    Filed: November 5, 2003
    Publication date: May 13, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Hideto Fukuda, Shinya Udo, Masao Kumagai, Osamu Kudo
  • Publication number: 20030142053
    Abstract: An integrated circuit includes a first signal-inversion switching circuit which receives a signal supplied from an exterior thereof as a first input signal, followed by outputting the first input signal after logic inversion thereof in response to a first state of a switching signal and outputting the first input signal without logic inversion in response to a second state of the switching signal, a signal processing circuit which performs signal processing based on the output of the first signal-inversion switching circuit, and a second signal-inversion switching circuit which receives the output of the first signal-inversion switching circuit passing through the signal processing circuit as a second input signal, followed by outputting the second input signal after logic inversion thereof in response to the second state of the switching signal and outputting the second input signal without logic inversion in response to the first state of the switching signal.
    Type: Application
    Filed: January 3, 2003
    Publication date: July 31, 2003
    Applicant: Fujitsu Limited
    Inventors: Masao Kumagai, Hideto Fukuda, Shinya Udo