Patents by Inventor Hidetoshi Fujimoto

Hidetoshi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190265050
    Abstract: A map data providing system stores map data including multiple section data in which a reference point indicated by absolute coordinates is set for each of multiple sections, and a map element is represented by relative coordinates to the reference point of the section to which the map element belongs, detects position coordinates of the vehicle based on a navigation signal, employs a difference between absolute coordinates of the map element indicated by the map data and absolute coordinates of the map element identified based on the relative position of the map element and the position coordinates of the vehicle as a deviation amount, calculates a correction amount based on the deviation amount, corrects the position information of the reference point by using the correction amount, and creates corrected map data indicating position coordinates of the map element.
    Type: Application
    Filed: May 8, 2019
    Publication date: August 29, 2019
    Inventor: Hidetoshi FUJIMOTO
  • Publication number: 20190258295
    Abstract: A flexible device includes at least a pair of magnets, and at least the pair of magnets are disposed such that a repelling force acts between the magnets when a display portion is folded opposing one part and the other part of the flexible display.
    Type: Application
    Filed: September 13, 2016
    Publication date: August 22, 2019
    Inventor: Hidetoshi FUJIMOTO
  • Publication number: 20190220061
    Abstract: An information processing device (11) includes, as a second connection section for connecting a first member (3) and a second member (4) with each other, a flexible hinge (19) that allows for rotation at least from (i) the angle at which a portion of a flexible display (7U) which portion is on the front surface of the second member (4) is in contact with a portion of the flexible display (7L) which portion is on the front surface of the first member (3) to (ii) the angle at which the portion of the flexible display (7U) which portion is on the front surface of the second member (4) is flush with the portion of the flexible display (7L) which portion is on the front surface of the first member (3).
    Type: Application
    Filed: September 1, 2016
    Publication date: July 18, 2019
    Inventor: Hidetoshi FUJIMOTO
  • Publication number: 20190212781
    Abstract: A flexible device includes a display portion including a flexible display and a support body. The support body includes at least one curved portion that includes a surface opposite from a laid surface of the flexible display, the surface being gently curved toward the laid surface of the flexible display, and that has an oval arc-shaped cross section. The flexible display is laid across the curved portion.
    Type: Application
    Filed: September 20, 2016
    Publication date: July 11, 2019
    Inventor: Hidetoshi FUJIMOTO
  • Patent number: 10254798
    Abstract: A display device includes a foldable case unit and a flexible display panel. The case unit includes an elongated connecting plate, and a lower case and an upper case coupled to the connecting plate via hinge parts, respectively. The upper case has a variable dimension in a y direction. In the opened case unit, the lower case, the connecting plate, and the upper case are aligned flush with one another in the y direction. In the folded case unit, the dimension of the upper case in the y direction is larger than the dimension in the opened case unit, and the display panel is accommodated in a space surrounded with the lower case, the connecting plate, and the upper case.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: April 9, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hidetoshi Fujimoto
  • Publication number: 20180205842
    Abstract: An image forming apparatus includes a housing in which an image forming section is contained and a paper output section into which a sheet of paper on which an image has been formed is ejected. The paper output section includes a paper output tray that supports the front side or back side of the sheet of paper, a back-end supporting member that supports a back end of the sheet of paper in a paper ejection direction, and a paper takeout slot through which the sheet of paper is taken out. The paper output section is provided at the outer edge of the interior of the housing. The housing has an external wall whose inner face side is used as the paper output tray. The paper takeout slot opens upward.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 19, 2018
    Inventors: YUKIO KANAOKA, MASAAKI AIDA, HIDETOSHI FUJIMOTO
  • Publication number: 20170322598
    Abstract: A display device (10) includes a foldable case unit (100) and a flexible display panel (200). The case unit (100) includes an elongated connecting plate (130), and a lower case (110) and an upper case (120) coupled to the connecting plate (130) via hinge parts (141 and 142), respectively. The upper case (120) has a variable dimension in a y direction. In the opened case unit (100), the lower case (110), the connecting plate (130), and the upper case (120) are aligned flush with one another in the y direction. In the folded case unit (100), the dimension of the upper case (120) in the y direction is larger than the dimension in the opened case unit (100), and the display panel (200) is accommodated in a space surrounded with the lower case (110), the connecting plate (130), and the upper case (120).
    Type: Application
    Filed: November 10, 2015
    Publication date: November 9, 2017
    Inventor: Hidetoshi FUJIMOTO
  • Patent number: 9412856
    Abstract: A semiconductor device includes a first and second nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger the first nitride semiconductor layer. Source and drain electrodes are formed spaced from each other on the second nitride semiconductor layer. A third nitride semiconductor layer is formed on the second nitride semiconductor layer between the source and drain electrodes. A gate electrode is formed on the third nitride semiconductor layer. The third nitride semiconductor layer comprises at least two first layers and at least one a second layer which has a lower p-type dopant concentration than the first layer. The second layer also has a band gap larger than the first layer. The lowermost layer and the uppermost layer in the third nitride semiconductor layer stack are the first layers.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi Fujimoto
  • Patent number: 9412857
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Wataru Saito, Toru Sugiyama
  • Patent number: 9412825
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida, Yukako Murakami, Takako Motai
  • Publication number: 20160079410
    Abstract: A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 17, 2016
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI
  • Patent number: 9165922
    Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Takeshi Uchihara, Naoko Yanase, Toshiyuki Naka, Tetsuya Ohno, Tasuku Ono
  • Publication number: 20150263152
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Takako MOTAI
  • Publication number: 20150263155
    Abstract: A semiconductor device includes a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than the first nitride semiconductor layer. Source and drain electrodes are provided on the second nitride semiconductor layer. A third nitride semiconductor layer is provided between the source electrode and the drain electrode on the second nitride semiconductor layer. The third nitride semiconductor layer has an impurity concentration of 1×1017 atoms/cm3 or less, and a band gap narrower than the second nitride semiconductor layer. A p-type fourth nitride semiconductor layer is provided on the third nitride semiconductor layer, and a gate electrode is provided on the fourth nitride semiconductor layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventor: Hidetoshi FUJIMOTO
  • Publication number: 20150263700
    Abstract: According to one embodiment, a semiconductor device includes a GaN-based semiconductor layer, a resonator that uses a first portion of the GaN-based semiconductor layer as a piezoelectric layer to resonate, and a transistor that uses a second portion of the GaN-based semiconductor layer as a channel layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Yoshikazu SUZUKI
  • Publication number: 20150263103
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer including a first nitride semiconductor, a second semiconductor layer on the first semiconductor layer including a second nitride semiconductor, a source electrode, a drain electrode, a first gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode having a schottky junction, a second gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the source electrode and the first gate electrode, electrically connected with the first gate electrode, and a third gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the drain electrode and the first gate electrode, electrically connected with the first gate electrode.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Takaaki Yasumoto, Naoko Yanase, Tasuku Ono
  • Publication number: 20150263101
    Abstract: In one embodiment, a semiconductor device includes a semiconductor chip including a nitride semiconductor layer, and including a control electrode, a first electrode and a second electrode provided on the nitride semiconductor layer. The device further includes a support including a substrate, and including a control terminal, a first terminal and a second terminal provided on the substrate. The semiconductor chip is provided on the support such that the control electrode, the first electrode and the second electrode face the support. The control electrode, the first electrode and the second electrode of the semiconductor chip are electrically connected to the control terminal, the first terminal and the second terminal of the support, respectively.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Shingo Masuko, Takaaki Yasumoto, Naoko Yanase, Miki Yumoto, Masahito Mimura, Yasunobu Saito, Akira Yoshioka, Hidetoshi Fujimoto, Takeshi Uchihara, Tetsuya Ohno, Toshiyuki Naka, Tasuku Ono
  • Publication number: 20150263001
    Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. A first control electrode is on the first semiconductor layer with a first insulating layer between the first control electrode and the first semiconductor layer. A second control electrode is on the first semiconductor layer with a second insulating layer between the second control electrode and the first semiconductor layer, a distance between the first control electrode and the first semiconductor layer is less than a distance between the second control electrode. A wiring electrically connects the first control electrode and the second control electrode.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Yasunobu SAITO, Hidetoshi FUJIMOTO, Akira YOSHIOKA, Takeshi UCHIHARA, Toshiyuki NAKA, Tasuku ONO
  • Publication number: 20150263154
    Abstract: A semiconductor device includes a first and second nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger the first nitride semiconductor layer. Source and drain electrodes are formed spaced from each other on the second nitride semiconductor layer. A third nitride semiconductor layer is formed on the second nitride semiconductor layer between the source and drain electrodes. A gate electrode is formed on the third nitride semiconductor layer. The third nitride semiconductor layer comprises at least two first layers and at least one a second layer which has a lower p-type dopant concentration than the first layer. The second layer also has a band gap larger than the first layer. The lowermost layer and the uppermost layer in the third nitride semiconductor layer stack are the first layers.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventor: Hidetoshi FUJIMOTO
  • Patent number: D815088
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 10, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hidetoshi Fujimoto