Patents by Inventor Hidetoshi Ishibashi

Hidetoshi Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11742251
    Abstract: A power semiconductor device includes: a power semiconductor element; a control circuit that controls the power semiconductor element; a control substrate having the control circuit mounted thereon; a lid arranged to overlap with at least a portion of the control substrate in a first direction; and at least one external connection terminal having a first portion connected with the control substrate, a second portion to be connected with an external apparatus, and a third portion located between the first portion and the second portion and fixed to the lid, the first portion being constituted as a press-fit portion.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: August 29, 2023
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Ishibashi, Yoshitaka Kimura, Minoru Egusa, Nobuhiro Asaji, Kazunari Teshigawara
  • Publication number: 20230228661
    Abstract: A test method of the present disclosure includes: applying a thermal grease on a support plate; placing a press plate such that the press plate faces the support plate with the thermal grease interposed between the press plate and the support plate; changing a distance between the support plate and the press plate; and observing a shape of the thermal grease after the distance between the support plate and the press plate is changed. The pumping-out performance is determined based on the shape of the thermal grease.
    Type: Application
    Filed: November 23, 2022
    Publication date: July 20, 2023
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hidetoshi ISHIBASHI, Ayumi MINAMIDE, Seiji OKA, Yurie FURUTA, Shunji MASUMORI
  • Publication number: 20220415738
    Abstract: A power semiconductor device in which the size of an insulating substrate is reduced and connection failure can be suppressed includes an insulating substrate, a semiconductor element, and a printed circuit board. The semiconductor element is bonded to one main surface of the insulating substrate. The printed circuit board is bonded to face the semiconductor element. The semiconductor element has a main electrode and a signal electrode. The printed circuit board includes a core member, a first conductor layer, and a second conductor layer. The second conductor layer has a bonding pad. The printed circuit board has a missing portion. A metal column portion is arranged to pass through the inside of the missing portion and reach the insulating substrate. The signal electrode and the bonding pad are connected by a metal wire. The metal column portion and the insulating substrate are bonded.
    Type: Application
    Filed: November 18, 2020
    Publication date: December 29, 2022
    Applicant: Mitsubishi Electric Corporation
    Inventors: Nobuhiro ASAJI, Kazuya OKADA, Hidetoshi ISHIBASHI
  • Patent number: 11424178
    Abstract: A semiconductor module includes: an insulated circuit board; a semiconductor device mounted on the insulated circuit board; a printed wiring board arranged above the insulated circuit board and the semiconductor device and having a through-hole; a metal pile having a lower end bonded to an upper surface of the semiconductor device and a cylindrical portion penetrating through the through-hole and bonded to the printed wiring board; a case surrounding the insulated circuit board, the semiconductor device, the printed wiring board and the metal pile; and a sealing material sealing an inside of the case.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: August 23, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Satoshi Kondo, Hidetoshi Ishibashi, Hiroshi Yoshida, Nobuhiro Asaji, Junji Fujino, Yusuke Ishiyama, Hodaka Rokubuichi
  • Patent number: 11404340
    Abstract: An upper conductor portion having a thickness A larger than a thickness B of a lower conductor portion, the upper conductor portion including a circuit pattern on which semiconductor chips are disposed and an outer peripheral pattern provided on an outer peripheral side of the circuit pattern at a certain gap, the outer peripheral pattern of the upper conductor portion, an outer peripheral portion of an insulating layer, and an outer peripheral portion of the lower conductor portion are fixed to a concave portion formed in the inner peripheral portion of the peripheral wall portion of a case, a collar portion projecting outward from the outer peripheral portion of the peripheral wall portion of the case is formed, and the attachment holes, through which the radiation fins are attachable, are formed in the collar portion.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: August 2, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Ishibashi, Hiroshi Yoshida
  • Patent number: 11329012
    Abstract: A technique for activating a fuse function in a semiconductor device in a relatively short time is provided. The semiconductor device includes a second bonding material provided on the upper surface of the insulating substrate, a third bonding material provided on an upper surface of the semiconductor element, a through hole extending from the first circuit pattern to the second circuit pattern via the core material, a conductive film provided on an inner wall of the through hole, and a heat insulating material provided inside the through hole and surrounded by the conductive film in plan view. The conductive film allows the first circuit pattern and the second circuit pattern to be conductive.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: May 10, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Kitabayashi, Hiroshi Yoshida, Hidetoshi Ishibashi, Daisuke Murata
  • Patent number: 11270982
    Abstract: A metal mask is disposed on a copper base plate. A solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste on each of copper plates of the copper base plate. A semiconductor element and a conductive component are placed on the respective patterns of the solder pastes. A metal mask is disposed on the copper base plate. Then, a solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste covering each of the semiconductor element and the conductive component. A large-capacity relay board is disposed so as to come into contact with a corresponding pattern of the solder paste. A power semiconductor device is completed by performing heat treatment under a temperature condition of 200° C. or higher.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: March 8, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Norikazu Sakai, Hiroshi Yoshida, Hidetoshi Ishibashi, Nobuhiro Asaji
  • Patent number: 11107760
    Abstract: According to the present invention, a semiconductor device includes an insulating substrate having an organic insulating layer and a circuit pattern provided on the organic insulating layer; and a semiconductor chip provided on an upper surface of the circuit pattern, wherein a thickness of the circuit pattern is not less than 1 mm and not more than 3 mm. According to the present invention, a method for manufacturing a semiconductor device includes forming a metal layer with a thickness not less than 1 mm and not more than 3 mm on an organic insulating layer; patterning the metal layer by machining processing to form a circuit pattern; and providing a semiconductor chip on an upper surface of the circuit pattern.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 31, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Murata, Hiroshi Yoshida, Hidetoshi Ishibashi
  • Publication number: 20210134686
    Abstract: A power semiconductor device includes: a power semiconductor element; a control circuit that controls the power semiconductor element; a control substrate having the control circuit mounted thereon; a lid arranged to overlap with at least a portion of the control substrate in a first direction; and at least one external connection terminal having a first portion connected with the control substrate, a second portion to be connected with an external apparatus, and a third portion located between the first portion and the second portion and fixed to the lid, the first portion being constituted as a press-fit portion.
    Type: Application
    Filed: August 14, 2020
    Publication date: May 6, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Ishibashi, Yoshitaka Kimura, Minoru Egusa, Nobuhiro Asaji, Kazunari Teshigawara
  • Publication number: 20210066175
    Abstract: A semiconductor module includes: an insulated circuit board; a semiconductor device mounted on the insulated circuit board; a printed wiring board arranged above the insulated circuit board and the semiconductor device and having a through-hole; a metal pile having a lower end bonded to an upper surface of the semiconductor device and a cylindrical portion penetrating through the through-hole and bonded to the printed wiring board; a case surrounding the insulated circuit board, the semiconductor device, the printed wiring board and the metal pile; and a sealing material sealing an inside of the case.
    Type: Application
    Filed: April 9, 2020
    Publication date: March 4, 2021
    Applicant: Mitsubishi Electric Corporation
    Inventors: Satoshi KONDO, Hidetoshi ISHIBASHI, Hiroshi YOSHIDA, Nobuhiro ASAJI, Junji FUJINO, Yusuke ISHIYAMA, Hodaka ROKUBUICHI
  • Patent number: 10790218
    Abstract: A semiconductor device according to the present invention includes a relay substrate provided on a plurality of semiconductor chips. The relay substrate includes an insulating plate in which a through hole is formed, a lower conductor provided on a lower surface of the insulating plate and having a first lower conductor and a second lower conductor, an upper conductor provided on an upper surface of the insulating plate, a connection part provided in the through hole and connecting the second lower conductor and the upper conductor together, and a protruding part which is a part of one of the first lower conductor and the upper conductor and protrudes outward from the insulating plate, the protruding part is connected to a first external electrode, and another of the first lower conductor and the upper conductor is connected to a second external electrode and is positioned inside the insulating plate.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: September 29, 2020
    Assignee: Mitsubishi Electric Corpration
    Inventors: Hidetoshi Ishibashi, Hiroshi Yoshida, Daisuke Murata, Takuya Kitabayashi
  • Patent number: 10770367
    Abstract: A semiconductor apparatus includes: a substrate including a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the substrate; a sealing material sealing the semiconductor device and the substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on a side face of the substrate.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: September 8, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Kitabayashi, Hiroshi Yoshida, Hidetoshi Ishibashi, Daisuke Murata
  • Publication number: 20200235060
    Abstract: A technique for activating a fuse function in a semiconductor device in a relatively short time is provided. The semiconductor device includes a second bonding material provided on the upper surface of the insulating substrate, a third bonding material provided on an upper surface of the semiconductor element, a through hole extending from the first circuit pattern to the second circuit pattern via the core material, a conductive film provided on an inner wall of the through hole, and a heat insulating material provided inside the through hole and surrounded by the conductive film in plan view. The conductive film allows the first circuit pattern and the second circuit pattern to be conductive.
    Type: Application
    Filed: October 16, 2019
    Publication date: July 23, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takuya KITABAYASHI, Hiroshi YOSHIDA, Hidetoshi ISHIBASHI, Daisuke MURATA
  • Publication number: 20200185295
    Abstract: An upper conductor portion having a thickness A larger than a thickness B of a lower conductor portion, the upper conductor portion including a circuit pattern on which semiconductor chips are disposed and an outer peripheral pattern provided on an outer peripheral side of the circuit pattern at a certain gap, the outer peripheral pattern of the upper conductor portion, an outer peripheral portion of an insulating layer, and an outer peripheral portion of the lower conductor portion are fixed to a concave portion formed in the inner peripheral portion of the peripheral wall portion of a case, a collar portion projecting outward from the outer peripheral portion of the peripheral wall portion of the case is formed, and the attachment holes, through which the radiation fins are attachable, are formed in the collar portion.
    Type: Application
    Filed: September 26, 2019
    Publication date: June 11, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hidetoshi ISHIBASHI, Hiroshi YOSHIDA
  • Publication number: 20200161233
    Abstract: According to the present invention, a semiconductor device includes an insulating substrate having an organic insulating layer and a circuit pattern provided on the organic insulating layer; and a semiconductor chip provided on an upper surface of the circuit pattern, wherein a thickness of the circuit pattern is not less than 1 mm and not more than 3 mm. According to the present invention, a method for manufacturing a semiconductor device includes forming a metal layer with a thickness not less than 1 mm and not more than 3 mm on an organic insulating layer; patterning the metal layer by machining processing to form a circuit pattern; and providing a semiconductor chip on an upper surface of the circuit pattern.
    Type: Application
    Filed: June 25, 2019
    Publication date: May 21, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Daisuke MURATA, Hiroshi YOSHIDA, Hidetoshi ISHIBASHI
  • Publication number: 20200083146
    Abstract: A semiconductor device according to the present invention includes a relay substrate provided on a plurality of semiconductor chips. The relay substrate includes an insulating plate in which a through hole is formed, a lower conductor provided on a lower surface of the insulating plate and having a first lower conductor and a second lower conductor, an upper conductor provided on an upper surface of the insulating plate, a connection part provided in the through hole and connecting the second lower conductor and the upper conductor together, and a protruding part which is a part of one of the first lower conductor and the upper conductor and protrudes outward from the insulating plate, the protruding part is connected to a first external electrode, and another of the first lower conductor and the upper conductor is connected to a second external electrode and is positioned inside the insulating plate.
    Type: Application
    Filed: May 7, 2019
    Publication date: March 12, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hidetoshi ISHIBASHI, Hiroshi YOSHIDA, Daisuke MURATA, Takuya KITABAYASHI
  • Publication number: 20190348404
    Abstract: A metal mask is disposed on a copper base plate. A solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste on each of copper plates of the copper base plate. A semiconductor element and a conductive component are placed on the respective patterns of the solder pastes. A metal mask is disposed on the copper base plate. Then, a solder paste is introduced into each of a plurality of openings in the metal mask, to thereby form a pattern of the solder paste covering each of the semiconductor element and the conductive component. A large-capacity relay board is disposed so as to come into contact with a corresponding pattern of the solder paste. A power semiconductor device is completed by performing heat treatment under a temperature condition of 200° C. or higher.
    Type: Application
    Filed: January 30, 2017
    Publication date: November 14, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Norikazu SAKAI, Hiroshi YOSHIDA, Hidetoshi ISHIBASHI, Nobuhiro ASAJI
  • Publication number: 20190304866
    Abstract: A semiconductor apparatus includes: an insulating substrate including a circuit pattern on an upper surface side and a metal plate on a lower surface side; a semiconductor device joined to the circuit pattern via a conductive component; a case located to surround the insulating substrate; a sealing material sealing the semiconductor device and the insulating substrate in a section surrounded by the case; and a bonding agent bonding the case and the metal plate on a side face of the insulating substrate.
    Type: Application
    Filed: October 15, 2018
    Publication date: October 3, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takuya KITABAYASHI, Hiroshi YOSHIDA, Hidetoshi ISHIBASHI, Daisuke MURATA
  • Patent number: 10388581
    Abstract: A semiconductor device includes an insulating substrate, a semiconductor element provided on the insulating substrate, a case frame, a press-fit terminal, and a sealing member provided on an inner side of an inner wall part on the insulating substrate to seal the semiconductor element. The case frame is made of an insulating material and includes an outer wall part, an inner wall part, a recess bottom surface forming a recess together with the outer wall part and the inner wall part. The press-fit terminal includes a base part, a body part, and a press-in portion. The base part is embedded in the recess bottom surface and the body part stands upright from the recess bottom surface such that the body part extends between the inner wall part and the outer wall part, and the press-in portion protrudes up out of the recess.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: August 20, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hidetoshi Ishibashi, Shinsuke Asada, Yoshitaka Kimura, Minoru Egusa
  • Publication number: 20190103330
    Abstract: A semiconductor device includes an insulating substrate, a semiconductor element provided on the insulating substrate, a case frame, a press-fit terminal, and a sealing member provided on an inner side of an inner wall part on the insulating substrate to seal the semiconductor element. The case frame is made of an insulating material and includes an outer wall part, an inner wall part, a recess bottom surface forming a recess together with the outer wall part and the inner wall part. The press-fit terminal includes a base part, a body part, and a press-in portion. The base part is embedded in the recess bottom surface and the body part stands upright from the recess bottom surface such that the body part extends between the inner wall part and the outer wall part, and the press-in portion protrudes up out of the recess.
    Type: Application
    Filed: April 23, 2018
    Publication date: April 4, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Hidetoshi ISHIBASHI, Shinsuke ASADA, Yoshitaka KIMURA, Minoru EGUSA