Patents by Inventor Hideya Murai
Hideya Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7566834Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23?5 (3) D150?2.5 (4) (D?65/D150)?3.0 (5) H23?140 (6) (H?65/H150)?2.3.Type: GrantFiled: June 16, 2008Date of Patent: July 28, 2009Assignees: NEC Corporation, NEC Electronics CorporationInventors: Tadanori Shimoto, Katsumi Kikuchi, Hideya Murai, Kazuhiro Baba, Hirokazu Honda, Keiichiro Kata
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Patent number: 7495734Abstract: An in-plane-switching liquid crystal display unit has a two-dimensional matrix of pixel regions each including a first auxiliary region and a second auxiliary region. When no electric field is applied, liquid crystal molecules in the first and second auxiliary regions are directed in respective orientations that lie at 90° with respect to each other. When a voltage is applied, the liquid crystal molecules are rotated in the same direction while maintaining their orientations in the first and second auxiliary regions at 90° with respect to each other. Alternatively, the liquid crystal molecules in the first and second auxiliary regions are directed in the same orientation when no electric field is applied, and when a voltage is applied, the liquid crystal molecules are rotated 15 opposite directions while maintaining their orientations in symmetric relationship.Type: GrantFiled: May 13, 2005Date of Patent: February 24, 2009Assignee: NEC CorporationInventors: Teruaki Suzuki, Shinichi Nishida, Hideya Murai, Masayoshi Suzuki, Makoto Watanabe, Yoshihiko Hirai
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Publication number: 20090046441Abstract: A wiring board for mounting semiconductor device, includes at least a dielectric film 1; wirings formed in the dielectric film 1; a plurality of electrode pads provided at front and back surfaces of the dielectric film with their surfaces exposed and at least portions of lateral sides of them buried into the dielectric film; vias connecting the wirings and the electrode pads. At least one via connecting each other the wirings formed in the dielectric film includes second material different from first material forming the vias connecting the wirings and the electrode pads. The wiring board for mounting semiconductor device, is effective for an increase in terminals and finer pitch of terminal intervals due to an improvement in integration, performance or multi-function of semiconductor devices, can mount semiconductor devices especially on both sides of the board at a high density and high accuracy, and furthermore, is excellent in reliability as well.Type: ApplicationFiled: December 20, 2006Publication date: February 19, 2009Applicants: Nec Corporation, Nec Electronics CorporationInventors: Takuo Funaya, Hideya Murai, Shintaro Yamamichi, Katsumi Kikuchi, Hirokazu Honda, Shinichi Miyazaki
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Publication number: 20090026636Abstract: Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.Type: ApplicationFiled: July 24, 2008Publication date: January 29, 2009Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Hideya MURAI, Kentaro Mori, Shintaro Yamamichi, Masaya Kawano, Takehiko Maeda, Kouji Soejima
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Publication number: 20090001604Abstract: An oxide layer and a metal layer composed of a gold- or platinum-group metal are formed in the stated order on a substrate. A wiring body having a wiring layer, insulating layer, via, and electrode is formed on the metal layer. A semiconductor element is then connected as a flip chip via solder balls on the wiring body electrode, and underfill is introduced between the semiconductor element and the wiring body. Subsequently, a sealing resin layer is formed so as to cover the semiconductor element and the surface of the wiring body on which the semiconductor element is mounted, thus producing a semiconductor package. A high-density, detailed, thin semiconductor package can thereby be realized.Type: ApplicationFiled: March 1, 2006Publication date: January 1, 2009Inventors: Daisuke Tanaka, Shintaro Yamamichi, Hideya Murai, Tadanori Shimoto, Kaichirou Nakano, Katsumi Maeda, Katsumi Kikuchi, Yoichiro Kurita, Kouji Soejima
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Publication number: 20080303136Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.Type: ApplicationFiled: June 9, 2008Publication date: December 11, 2008Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Kentaro Mori, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Masaya Kawano, Takehiko Maeda, Kouji Soejima
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Publication number: 20080258283Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23?5 (3) D150?2.5 (4) (D?65/D150)?3.0 (5) H23?140 (6) (H?65/H150)?2.Type: ApplicationFiled: June 16, 2008Publication date: October 23, 2008Applicants: NEC CORPORATION, NEC ELECTRONICS CORPORATIONInventors: Tadanori SHIMOTO, Katsumi KIKUCHI, Hideya MURAI, Kazuhiro BABA, Hirokazu HONDA, Keiichiro KATA
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Patent number: 7397000Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less (2) D23?5 (3) D150?2.5 (4) (D?65/D150)?3.0 (5) H23?140 (6) (H?65/H150)?2.3.Type: GrantFiled: May 10, 2005Date of Patent: July 8, 2008Assignees: NEC Corporation, NEC Electronics CorporationInventors: Tadanori Shimoto, Katsumi Kikuchi, Hideya Murai, Kazuhiro Baba, Hirokazu Honda, Keiichiro Kata
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Patent number: 7348673Abstract: A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25° C.Type: GrantFiled: July 14, 2005Date of Patent: March 25, 2008Assignees: NEC Corporation, NEC Electronics CorporationInventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Hirokazu Honda, Koji Soejima, Shinichi Miyazaki
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Patent number: 7294393Abstract: In a sheet material (1), a bonding layer (2) is provided, and then a high-strength layer (3) is laminated on the bonding layer (2). The bonding layer (2) is made of an epoxy resin being a thermosetting material. The high-strength layer (3) is made of polyimide, which is not softened at a thermosetting temperature of the epoxy resin and has a tensile rupture strength higher than that of the cured thermosetting material. Moreover, the polyimide has a tensile rupture strength of 100 MPa or higher at 23° C. and a tensile rupture elongation of 10% or higher at 23° C. Assuming that a tensile rupture strength at ?65° C. is a and a tensile rupture strength at 150° C. is b, a ratio (a/b) is 2.5 or less.Type: GrantFiled: June 27, 2005Date of Patent: November 13, 2007Assignee: NEC CorporationInventors: Hideya Murai, Tadanori Shimoto, Kazuhiro Baba, Katsumi Kikuchi
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Publication number: 20060283625Abstract: A wiring board in which lower-layer wiring composed of a wiring body and an etching barrier layer is formed in a concave portion formed on one face of a board-insulating film, upper-layer wiring is formed on the other face of the board-insulating film, and the upper-layer wiring and the wiring body of the lower-layer wiring are connected to each other through a via hole formed in the board-insulating film. The via hole is barrel-shaped, bell-shaped, or bellows-shaped.Type: ApplicationFiled: June 15, 2006Publication date: December 21, 2006Inventors: Shintaro Yamamichi, Katsumi Kikuchi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Kenta Ogawa, Jun Tsukano, Hirokazu Honda
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Publication number: 20060283629Abstract: A wiring board for mounting a semiconductor element or electronic component having a plurality of wiring layers, an insulating layer provided between these wiring layers, and a via which is provided to the insulating layer and which electrically connects the wiring layers. In this wiring board, the cross-sectional shape of the via in the plane parallel to the wiring layers is obtained by the partial overlapping of a plurality of similar shapes (circles). Stable operation can be obtained in a semiconductor element by minimizing obstacles to increased density, effectively increasing the cross-sectional area of the via, and preventing the wiring resistance from increasing by making the cross-sectional shape of the via into a shape obtained by the partial overlapping of a plurality of similar shapes.Type: ApplicationFiled: June 9, 2006Publication date: December 21, 2006Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
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Publication number: 20060012029Abstract: A minute wiring structure portion including first wiring layers and first insulating layers, in which each of first wiring layers and each of first insulating layers are alternately laminated, is formed on a semiconductor substrate. A first huge wiring structure portion is formed on the minute wiring structure portion, and the first huge wiring structure portion is formed by successively forming on the minute wiring structure portion, in the following order, the first huge wiring portion including second wiring layers has a thickness of twice or more of the thickness of the first wiring layers and second insulating layers, in which each of second wiring layers and each of second wiring layers are alternately laminated, and a second huge wiring structure portion including third wiring layers has a thickness of twice or more of the thickness of the first wiring layer and a third insulating layer in which the elastic modulus at 25° C.Type: ApplicationFiled: July 14, 2005Publication date: January 19, 2006Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Hirokazu Honda, Koji Soejima, Shinichi Miyazaki
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Publication number: 20060012048Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.Type: ApplicationFiled: July 6, 2005Publication date: January 19, 2006Inventors: Hideya Murai, Tadanori Shimoto, Takuo Funaya, Katsumi Kikuchi, Shintaro Yamamichi, Kazuhiro Baba, Hirokazu Honda, Keiichiro Kata, Kouji Matsui, Shinichi Miyazaki
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Patent number: 6987551Abstract: An in-plane-switching liquid crystal display unit has a two-dimensional matrix of pixel regions each including a first auxiliary region and a second auxiliary region. When no electric field is applied, liquid crystal molecules in the first and second auxiliary regions are directed in respective orientations that lie at 90° with respect to each other. When a voltage is applied, the liquid crystal molecules are rotated in the same direction while maintaining their orientations in the first and second auxiliary regions at 90° with respect to each other. Alternatively, the liquid crystal molecules in the first and second auxiliary regions are directed in the same orientation when no electric field is applied, and when a voltage is applied, the liquid crystal molecules are rotated opposite directions while maintaining their orientations in symmetric relationship.Type: GrantFiled: January 24, 2003Date of Patent: January 17, 2006Assignee: NEC CorporationInventors: Teruaki Suzuki, Shinichi Nishida, Hideya Murai, Masayoshi Suzuki, Makoto Watanabe, Yoshihiko Hirai
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Publication number: 20050281995Abstract: In a sheet material (1), a bonding layer (2) is provided, and then a high-strength layer (3) is laminated on the bonding layer (2). The bonding layer (2) is made of an epoxy resin being a thermosetting material. The high-strength layer (3) is made of polyimide, which is not softened at a thermosetting temperature of the epoxy resin and has a tensile rupture strength higher than that of the cured thermosetting material. Moreover, the polyimide has a tensile rupture strength of 100 MPa or higher at 23° C. and a tensile rupture elongation of 10% or higher at 23° C. Assuming that a tensile rupture strength at ?65° C. is a and a tensile rupture strength at 150° C. is b, a ratio (a/b) is 2.5 or less.Type: ApplicationFiled: June 27, 2005Publication date: December 22, 2005Inventors: Hideya Murai, Tadanori Shimoto, Kazuhiro Baba, Katsumi Kikuchi
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Publication number: 20050264743Abstract: An in-plane-switching liquid crystal display unit has a two-dimensional matrix of pixel regions each including a first auxiliary region and a second auxiliary region. When no electric field is applied, liquid crystal molecules in the first and second auxiliary regions are directed in respective orientations that lie at 90° with respect to each other. When a voltage is applied, the liquid crystal molecules are rotated in the same direction while maintaining their orientations in the first and second auxiliary regions at 90° with respect to each other. Alternatively, the liquid crystal molecules in the first and second auxiliary regions are directed in the same orientation when no electric field is applied, and when a voltage is applied, the liquid crystal molecules are rotated 15 opposite directions while maintaining their orientations in symmetric relationship.Type: ApplicationFiled: May 13, 2005Publication date: December 1, 2005Inventors: Teruaki Suzuki, Shinichi Nishida, Hideya Murai, Masayoshi Suzuki, Makoto Watanabe, Yoshihiko Hirai
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Publication number: 20050252682Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23?5 (3) D150?2.5 (4) (D-65/D150)?3.0 (5) H23?140 (6) (H-65/H150)?2.Type: ApplicationFiled: May 10, 2005Publication date: November 17, 2005Inventors: Tadanori Shimoto, Katsumi Kikuchi, Hideya Murai, Kazuhiro Baba, Hirokazu Honda, Keiichiro Kata
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Publication number: 20040089470Abstract: A printed circuit board is provided including a lower interconnect, a base insulating film formed on the lower interconnect, and a via hole formed on the base insulating film, and an upper interconnect connected to the lower interconnect with the via hole. The base insulating film has a thickness of about 3 to 100 &mgr;m and has a breaking strength of about 80 MPa or more at a temperature of 23° C. and when the base insulating film is defined to have a breaking strength “a” at a temperature of −65° C. and a breaking strength “b” at a temperature of 150° C., a value of a ratio (a/b) is about 4.5 or less.Type: ApplicationFiled: November 6, 2003Publication date: May 13, 2004Applicant: NEC CORPORATIONInventors: Tadanori Shimoto, Hirokazu Honda, Keiichiro Kata, Hideya Murai, Katsumi Kikuchi, Kazuhiro Baba
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Publication number: 20030133068Abstract: An in-plane-switching liquid crystal display unit has a two-dimensional matrix of pixel regions each including a first auxiliary region and a second auxiliary region. When no electric field is applied, liquid crystal molecules in the first and second auxiliary regions are directed in respective orientations that lie at 90° with respect to each other. When a voltage is applied, the liquid crystal molecules are rotated in the same direction while maintaining their orientations in the first and second auxiliary regions at 90° with respect to each other. Alternatively, the liquid crystal molecules in the first and second auxiliary regions are directed in the same orientation when no electric field is applied, and when a voltage is applied, the liquid crystal molecules are rotated opposite directions while maintaining their orientations in symmetric relationship.Type: ApplicationFiled: January 24, 2003Publication date: July 17, 2003Applicant: NEC CORPORATIONInventors: Teruaki Suzuki, Shinichi Nishida, Hideya Murai, Masayoshi Suzuki, Makoto Watanabe, Yoshihiko Hirai