Patents by Inventor Hideyuki Funaki
Hideyuki Funaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9407221Abstract: In one embodiment, a differential amplifier circuit includes a first input terminal, a second input terminal, a first transistor, a second transistor, a third transistor, a current source, a first output terminal, a second output terminal, a first passive element, and a second passive element. The first (second) transistor has a control terminal connected to the first (second) input terminal. The third transistor has a control terminal. The control terminal is applied predetermined bias voltage. The current source is connected to a first terminal in each of the first transistor, second transistor, and third transistor. The first (second) output terminal is connected to a second terminal of the first (second) transistor. The first (second) passive element is connected between the first (second) input terminal and the first (second) output terminal.Type: GrantFiled: October 30, 2014Date of Patent: August 2, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuro Itakura, Masanori Furuta, Shunsuke Kimura, Go Kawata, Hideyuki Funaki
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Publication number: 20160211830Abstract: A waveform shaping filter according to one embodiment includes a first resistor, a first transistor, a first capacitor, and a first amplifier. The first resistor includes one end to which a signal current is input and the other end. The first transistor includes a first terminal connected to the other end of the first resistor, a second terminal, and a control terminal. The first capacitor includes one end connected to the other end of the first resistor and the other end. The first amplifier includes an input terminal connected to the one end of the first resistor and an output terminal connected to the control terminal of the first transistor.Type: ApplicationFiled: January 19, 2016Publication date: July 21, 2016Inventors: Tetsuro ITAKURA, Masanori FURUTA, Shunsuke KIMURA, Hideyuki FUNAKI, Go KAWATA, Hirokatsu SHIRAHAMA
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Patent number: 9383549Abstract: According to an embodiment, an imaging system includes an image sensor, an imaging lens, a microlens array, an irradiator, a distance information acquiring unit, and a controller. The microlens array includes multiple microlenses arranged with a predetermined pitch, the microlenses being respectively associated with pixel blocks. The irradiator emits light to project a pattern onto an object. The distance information acquiring unit acquires information on the distance in the depth direction to the object on the basis of a signal resulting from photoelectric conversion performed by the image sensor. The controller controls the irradiator so that images contained in a pattern that is reflected by the object and scaled down on the image sensor by the imaging lens and the microlenses are smaller than the arrangement pitch of images each formed on the image sensor by each microlens and larger than twice the pixel.Type: GrantFiled: March 6, 2015Date of Patent: July 5, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Risako Ueno, Kazuhiro Suzuki, Mitsuyoshi Kobayashi, Honam Kwon, Hideyuki Funaki
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Patent number: 9377540Abstract: A radiation detection apparatus according to an embodiment includes: a scintillator; a photon detection device array including a plurality of cells each being a photon detection device with an avalanche photodiode configured to detect visible radiation photons emitted from the scintillator and a resistor disposed along a part of a periphery of an active region of the avalanche photodiode; and a reflector configured to reflect a visible radiation photon and disposed in a region that does not include the active regions and the resistors of the cells, on a face including the active regions.Type: GrantFiled: April 23, 2015Date of Patent: June 28, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Go Kawata, Hideyuki Funaki, Honam Kwon, Risako Ueno, Kazuhiro Suzuki
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Patent number: 9355283Abstract: An integration circuit according to one embodiment includes a first capacitance element, a capacitance circuit, a comparison circuit, a memory circuit and an operation circuit. The first capacitance element receives a current signal. The capacitance circuit includes a first switch and a second capacitance element, and is connected in parallel to the first capacitance element. The second capacitance element receives a current signal via the first switch. The comparison circuit compares a voltage of the first capacitance element with a reference voltage to obtain a comparison result. The memory circuit stores the comparison result, and opens or closes the first switch based on the comparison result. The operation circuit outputs a residual signal based on a difference between the integrated value obtained by the first capacitance element and the second capacitance element and a value based on the comparison result.Type: GrantFiled: May 22, 2015Date of Patent: May 31, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuro Itakura, Masanori Furuta, Shunsuke Kimura, Hideyuki Funaki, Go Kawata
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Patent number: 9344661Abstract: According to an embodiment, a photodetector includes a plurality of photoelectric transducers, a plurality of resistors, and a plurality of resetting sections. Each of the photoelectric transducers is configured to output a detection signal resulting from conversion of received light into an electric charge. Each of the resistors is connected in series with an output end of a corresponding photoelectric transducer at one end of the resistor. Each of the resetting sections is connected in parallel with a corresponding resistor and configured to bring the output end of the corresponding photoelectric transducer to a reset level in response to the detection signal.Type: GrantFiled: April 9, 2015Date of Patent: May 17, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Nobuyoshi Saito, Hideyuki Funaki, Shunsuke Kimura, Shintaro Nakano, Go Kawata, Rei Hasegawa
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Patent number: 9331125Abstract: According to one embodiment, a solid-state imaging device includes: a first inorganic photoelectric converter; a semiconductor substrate that includes a light-receiving face to which light is to be incident and a circuit-formed surface on which a circuit including a readout circuit is formed, the light-receiving face facing the first inorganic photoelectric converter, the semiconductor substrate including a second inorganic photoelectric converter thereinside; and a first part including a microstructure arranged between the first inorganic photoelectric converter and the second inorganic photoelectric converter.Type: GrantFiled: November 28, 2014Date of Patent: May 3, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Miyazaki, Ikuo Fujiwara, Hideyuki Funaki
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Patent number: 9300885Abstract: A solid state imaging device according to an embodiment includes: an imaging element formed on a semiconductor substrate, and including pixel blocks each having pixels; a main lens forming an image of a subject on an imaging plane; a microlens array including microlenses corresponding to the pixel blocks, the microlens array reducing an image to be formed on the imaging plane by Nf times or less and forming reduced images on the pixel blocks corresponding to the respective microlenses; and an image processing unit enlarging and synthesizing the reduced images formed by the microlenses, the solid state imaging device meeting conditions of an expression MTFMain(u)?MTFML(u)?MTFMain(u×Nf) where u denotes an image spatial frequency, MTFML(u) denotes an MTF function of the microlenses, and MTFMain(u) denotes an MTF function of the main lens.Type: GrantFiled: January 23, 2014Date of Patent: March 29, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Risako Ueno, Hiroto Honda, Mitsuyoshi Kobayashi, Kazuhiro Suzuki, Honam Kwon, Hideyuki Funaki
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Publication number: 20160084964Abstract: According to an embodiment, a photon detecting element includes one or more avalanche photodiodes and a circuit. The circuit is connected between cathodes of the one or more avalanche photodiodes and an external power source. The circuit is configured in which a first temperature coefficient representing variation of a setting potential with respect to temperature variation when constant-current driving is performed so that electrical potential of the cathodes becomes equal to the setting potential is substantially the same as a second temperature coefficient representing variation of breakdown voltage of the one or more avalanche photodiodes with respect to temperature variation.Type: ApplicationFiled: September 9, 2015Publication date: March 24, 2016Inventors: Shunsuke KIMURA, Hiroshi OTA, Go KAWATA, Hideyuki FUNAKI, Rei HASEGAWA
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Publication number: 20160077148Abstract: According to an embodiment, a signal processing device includes a first integrator, a second integrator, a switcher, and a calculator. The first integrator is configured to integrate a current represented by a reference waveform equivalent to a normal waveform in a case of no pileup phenomenon regarding the current to calculate a first electrical charge. The second integrator is configured to integrate a current output from a photoelectric converter to calculate a second electrical charge. The switcher is configured to, when a pileup phenomenon has occurred, perform switching either to a state in which the first and second electrical charges are output or to a state in which the first electrical charge and a reference charge are output. The calculator is configured to calculate a first difference charge between the first and second electrical charges, and calculate a second difference charge between the first electrical charge and the reference charge.Type: ApplicationFiled: September 4, 2015Publication date: March 17, 2016Inventors: Shunsuke KIMURA, Hideyuki FUNAKI
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Publication number: 20160079464Abstract: According to a photodetector includes a first light detection layer and a reflective layer. The first light detection layer has a first surface and a second surface on a side opposite to the first surface. The first light detection layer includes a first light detection area including a p-n junction of a p-type semiconductor layer containing Si and an n-type semiconductor layer containing Si. The reflective layer arranged on a second surface side of the first light detection layer so as to be opposed to the first light detection area. The reflective layer reflects at least part of light in a near-infrared range.Type: ApplicationFiled: August 31, 2015Publication date: March 17, 2016Inventors: Keita SASAKI, Risako UENO, Hideyuki FUNAKI
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Publication number: 20160079293Abstract: An infrared sensor according to an embodiment includes a housing, a detector, a lid, and a light shielding film. The detector is mounted on the bottom surface of the housing and includes a heat-sensitive pixel region and a reference pixel region. The lid seals the housing and includes a support member and a window member. The support member is bonded to the side surfaces of the housing and has an opening positioned above the heat-sensitive pixel region. The window member is bonded to a surface of the support member on a side of the detector so as to cover the opening. The light shielding film is formed on a surface of the window member on a side of the detector and arranged on an optical path of the infrared rays entering the reference pixel region.Type: ApplicationFiled: September 3, 2015Publication date: March 17, 2016Inventors: Koichi ISHII, Hideyuki Funaki
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Patent number: 9284186Abstract: After a TEOS oxide film is formed on the surface of a semiconductor device, a PSG film and an SiN film, which have air permeability, are formed on the surface of the TEOS oxide film. Thereafter, a Poly-Si film is formed thereon. A sacrifice layer is removed by a gaseous HF that passes through the PSG film, the SiN film, and the Poly-Si film, and then, the uppermost layer is covered with a Poly-Si/SiC film. A chip scale package having a thin-film hollow-seal structure can be realized on the semiconductor element.Type: GrantFiled: September 24, 2012Date of Patent: March 15, 2016Assignees: Kabushiki Kaisha Toshiba, The Regents of the University of CaliforniaInventors: Hiroshi Yamada, Hideyuki Funaki, Kazuhiro Suzuki, Kazuhiko Itaya, Armon Mahajerin, Kevin Limkrailassiri, Liwei Lin
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Publication number: 20160045176Abstract: According to an embodiment, a photon counting CT apparatus includes a scintillator, a photodiode array, a holder, a divider, and an image generator. The scintillator is configured to convert X-rays into light. The array includes first and second pixels. The first pixel includes a photodiode in a first range receiving the light emitted from the scintillator. The photodiode outputs an electrical signal based on the light. The second pixel includes a photodiode in a second range different from the first range. The holder is circuitry configured to hold a value of an electrical signal output by the second pixel. The divider circuitry is configured to count the number of photons of light incident on the first pixel by dividing an integrated value of electrical signals output by the first pixel by the held value. The image generator is circuitry configured to reconstruct an image based on the counted number.Type: ApplicationFiled: October 26, 2015Publication date: February 18, 2016Applicants: Kabushiki Kaisha Toshiba, Toshiba Medical Systems CorporationInventors: Shunsuke KIMURA, Hideyuki Funaki, Go Kawata
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Patent number: 9257156Abstract: There is provided an electromagnetic wave signal processor configured to process an input pulse signal corresponding to an electromagnetic wave, comprising a signal processing unit including: a peak detecting circuit to detect peak values of each amplitude of the input pulse signal; an AD converter to convert the peak values into digital signals; a memory device comprising memory cells each having an address assigned in accordance with each of values capable of being taken by the digital signals of the peak values, and being able to have any one of a plurality of internal states representing detection frequencies of the peak values; and a writing circuit to change the internal state in the memory cell that has the address corresponding to the value of each digital signal converted by the AD converter, so as to increment the detection frequency represented by the internal state.Type: GrantFiled: June 9, 2014Date of Patent: February 9, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Shunsuke Kimura, Hideyuki Funaki
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Patent number: 9257470Abstract: According to one embodiment, an imaging lens includes a first optical system and a microlens array. The first optical system includes an optical axis. The microlens array is provided between the first optical system and an imaging element. The microlens array includes microlens units provided in a first plane. The imaging element includes pixel groups. Each of the pixel groups includes pixels. The microlens units respectively overlap the pixel groups when projected onto the first plane. The first optical system includes an aperture stop, and first, second, and third lenses. The first lens is provided between the aperture stop and the microlens array, and has a positive refractive power. The second lens is provided between the first lens and the microlens array, and has a negative refractive power. The third lens is provided between the second lens and the microlens array, and has a positive refractive power.Type: GrantFiled: August 15, 2014Date of Patent: February 9, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Risako Ueno, Hiroto Honda, Mitsuyoshi Kobayashi, Kazuhiro Suzuki, Honam Kwon, Hideyuki Funaki
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Patent number: 9207365Abstract: According to one embodiment, an imaging lens includes a first optical system and a microlens array. The first optical system includes an optical axis. The microlens array is provided between the first optical system and an imaging element. The microlens array includes microlens units provided in a first plane. The imaging element includes pixel groups. Each of the pixel groups includes pixels. The microlens units respectively overlap the pixel groups when projected onto the first plane. The first optical system includes an aperture stop, a first lens, a second lens, a third lens, and a fourth lens. The first lens is provided between the aperture stop and the microlens array. The second lens is provided between the first lens and the microlens array. The third lens is provided between the second lens and the microlens array. The fourth lens is provided between the third lens and the microlens array.Type: GrantFiled: August 15, 2014Date of Patent: December 8, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Risako Ueno, Hiroto Honda, Mitsuyoshi Kobayashi, Kazuhiro Suzuki, Honam Kwon, Hideyuki Funaki
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Publication number: 20150349753Abstract: An integration circuit according to one embodiment includes a first capacitance element, a capacitance circuit, a comparison circuit, a memory circuit and an operation circuit. The first capacitance element receives a current signal. The capacitance circuit includes a first switch and a second capacitance element, and is connected in parallel to the first capacitance element. The second capacitance element receives a current signal via the first switch. The comparison circuit compares a voltage of the first capacitance element with a reference voltage to obtain a comparison result. The memory circuit stores the comparison result, and opens or closes the first switch based on the comparison result. The operation circuit outputs a residual signal based on a difference between the integrated value obtained by the first capacitance element and the second capacitance element and a value based on the comparison result.Type: ApplicationFiled: May 22, 2015Publication date: December 3, 2015Inventors: Tetsuro ITAKURA, Masanori FURUTA, Shunsuke KIMURA, Hideyuki FUNAKI, Go KAWATA
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Publication number: 20150324992Abstract: A solid-state imaging device according to an embodiment includes: an imaging element formed on a semiconductor substrate, and comprising an imaging region including a plurality of pixel blocks each including a plurality of pixels; a first optical system forming an image of an object on an imaging plane; and a second optical system comprising a microlens array including a plurality of microlenses each corresponding to one of the pixel blocks, and reducing and re-forming the image to be formed on the imaging plane on the pixel blocks corresponding to the respective microlenses. The imaging plane of the first optical system is located further away from the first optical system than the imaging element when the object is located at an infinite distance.Type: ApplicationFiled: May 29, 2015Publication date: November 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Risako UENO, Hideyuki FUNAKI, Mitsuyoshi KOBAYASHI
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Patent number: 9177989Abstract: A solid state imaging device according to an embodiment includes a photo detector arranged two-dimensionally in a semiconductor substrate, a readout circuit provided in the semiconductor substrate, a first photoelectric conversion layer provided above the photo detector, a plurality of first metal dots provided above the first photoelectric conversion layer, a second photoelectric conversion layer provided above the first metal dots, and a plurality of second metal dots provided above the second photoelectric conversion layer.Type: GrantFiled: March 13, 2013Date of Patent: November 3, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Ikuo Fujiwara, Hideyuki Funaki, Kenji Todori, Akira Fujimoto, Tsutomu Nakanishi, Kenji Nakamura