Abstract: A semiconductor memory device includes a plurality of input/output terminals (I/O1 to I/O4), a plurality of memory cell groups (1 to 4) and a plurality of sense amplifiers (31 to 34). A plurality of decision circuits (81 to 84) and a plurality of selection circuits (91 to 94) are provided in association with the input/output terminals (I/O1 to I/O4). A high voltage is applied to the input/output terminals that are not in use. This fixedly sets the corresponding sense amplifier groups to the non-activated state by means of the corresponding decision circuit and the selection circuit.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1,/.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1, /.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.

Abstract: An improved output driver circuit for a semiconductor integrated circuit device is provided. The output driver circuit receives a type select signal (.phi.1, /.phi.1) determined by bonding selection. When a heavy load circuit is connected to an output terminal (DQ), a signal (.phi.1) of low level and a signal (/.phi.1) of high level are provided, whereby transistors (18, 19) are turned on simultaneously in response to a data signal (Mo). When a light load circuit is connected to the terminal (DQ), a signal (.phi.1) of high level and a signal (/.phi.1) of low level are provided, whereby transistors (18, 19) are turned on at a different timing. More specifically, following charging of a light load by a transistor (18) having low mutual conductance, a transistor (19) is turned on. Therefore, noise generation can be flexibly suppressed by bonding selection.

Abstract: A bit line control circuit is disclosed for implementing a dynamic content addressable memory. The bit line control circuit includes a read circuit 12 and a first write circuit 13 connected to data line pairs DT, /DT, a sense amplifier 14, a bit line discharge circuit 15, a bit line charge circuit 16, a transfer gate circuit 17, and a second write circuit 18. The bit line control circuit is connected to a CAM cell array through bit lines BLa, /BLa. Various operations such as write, read, refresh and match detection and the like necessary in the dynamic associative memory can be implemented under simple timing control by a simple circuit configuration.

Abstract: In a semiconductor memory device capable of nibble mode operation, the time period required from the time when CAS signal falls to the time when a data output buffer activating signal rises is made different at the time of a normal mode and at the time of a nibble mode, so that the time period required for reading out data in the nibble mode is reduced as compared with a conventional device.

Abstract: A semiconductor memory device includes a plurality of operation mode control circuits provided on a memory chip of the device for respectively executing a corresponding plurality of writing/reading operation modes including at least a static column mode, a high speed page mode and a nibble mode, and a plurality of operation mode selection circuits provided on the memory chip, each of the operation mode selection circuits having a fuse element and a bonding pad for selecting one of the plurality of the operation mode control circuits when the fuse element is cut off or the bonding pad is selectively wired, so that various functions can be selectively effected on the same chip.

Abstract: A semiconductor device formed on a semiconductor chip (1) comprises a plurality of first bonding pads (3a, 3d) for receiving an identical external signal, an internal circuit (8) connected to any one of the plurality of the first bonding pads, a second bonding pad (11) for receiving a control signal from outside the semiconductor chip, and a bonding pad selection switch (19) for selecting a bonding pad out of the plurality of first bonding pads and connecting it to the internal circuit in response to the control signal supplied thereto through the second bonding pad.

Abstract: In a semiconductor memory device comprising a memory cell array and array control circuit for controlling the memory cell array and being operable in a page mode or a nibble mode, a mode selection circuit is provided for selective connection for operation in the page mode or for operation in the nibble mode. The mode selection circuit of the invention comprises fuse means which can be blown or left unblown for the selective connection.

Abstract: A semiconductor memory device with a laser programmable redundancy circuit, which includes: a plurality of decoders for selecting a row or column of the memory; at least one spare decoder which is selected instead of a decoder connected to a faulty memory cell; a link element inserted in series with the precharging transistor and connected between the power supply and the decoder output line; a signal generator which generates a non-selection signal for making the object decoder unselected only when a spare decoder is selected, the signal generator being provided in the spare decoder; and a transistor, having a gate to which the non-selection signal is input, with the drain and the source thereof being connected to the decoder output and ground, respectively, the transistor being provided in the decoder.

Abstract: A semiconductor memory device in which at least a line decoder or a column decoder in multiplex form is provided to select one line selection signal or column selection signal. When the line decoder or column decoder is defective, or when the word line or bit line associated with the line decoder or column decoder involves a defective bit, the defective line decoder, column decoder, word line or bit line is inactivated. The inactivated line decoder or column decoder is replaced with an auxiliary line decoder or column decoder.

Abstract: An MOS dynamic memory device is improved in operation by adding a cell plate voltage control circuit to terminals of the word lines and connected to respective cell plates. In operation, the cell plate is recharged after discharged during with a time which a word line remains driven.

Abstract: Disclosed is a semiconductor memory device which is operable in a selected one of page mode and nibble mode, depending upon the length of time in which an external column address strobe signal stays at a specific level. The semiconductor memory device comprises a circuit for discriminating the length of time where the external column address strobe signal is at a specific level with a predetermined period of time. Data is outputted in page mode in response to one of results of such discrimination and in nibble mode in response to the other result of the discrimination. The discriminating circuit may comprise a second internal column address strobe signal generator and a delay circuit. The second internal column address strobe signal generator includes a NAND circuit at its first stage, and the delay circuit is designed to have different delay times at the building-up and downward edges of an input signal applied thereto.

Abstract: Disclosed is a semiconductor memory device which is one of three types of semiconductor memory devices, one operable only in page mode, one operable only in nibble and one operable selectively in page mode or nibble mode, being obtained from a partially unconnected semiconductor memory device through alternations in a portions in wiring. The semiconductor memory device includes first and second internal column address strobe signal generator. The second internal column address strobe signal generator has at the first stage thereof a NAND circuit one of inputs to which determines the type of the semiconductor memory device depending on which of three kinds of signals is selected as the input. Selection of such an input is effected by an aluminum wiring process using a mask. Such selection of the input causes variation in the input response characteristics of the output of the second internal column address strobe signal generator, thus providing a desired response appropriate for the selected mode or modes.

Abstract: A semiconductor memory device having two layers of polycrystal silicon and having an insulated gate field effect transistor as a fundamental element including by using a first layer of polycrystalline silicon serving as an electrode of a capacitor and a bit line and a second layer of polycrystalline silicon serving as a gate electrode of the transistor.

Abstract: An input protective circuit of MIS type device is used by applying reverse bias voltage to a semiconductor substrate and a variable-conductivity element is connected between the input terminal of the MIS type device and the ground so that the input terminal is in conductive state to the ground when the reverse bias voltage is not applied to the semiconductor substrate and the input terminal is in non-conductive state to the ground when the reverse bias voltage is applied to the semiconductor substrate.

Abstract: The disclosure described a substrate bias generating circuit in which an internal RAS (Row Address Strobe) signal and an internal CAS (Column Address Strobe) signal, both of which are synchronized with an external RAS signal and external CAS supplied from outside in addition to self-oscillator, activate circuits comprising capacitors and rectifying elements respectively so as to reduce wattage dissipation thereof during holding time of RAM and be obtained increased charge pump current during operation thereof.

Abstract: The disclosure described a substrate bias generating circuit in which an internal RAS (Row Address Strobe) signal and an internal CAS (Column Address Strobe) signal, both of which are synchronized with an external RAS signal and external CAS supplied from outside in addition to self-oscillator, activate circuits .[.comprising.]. .Iadd.including .Iaddend.capacitors and rectifying elements respectively so as to reduce wattage dissipation thereof during holding time of RAM and be obtained increased charge pump current during operation thereof.