Abstract: The present disclosure generally relates to methods and systems for allocating free blocks as decommissioned blocks to replace bad blocks. In certain embodiments, when there are insufficient free blocks in a free block list to replace a bad or defective block for a CE, an FTL scans blocks stored in an unallocated block repository. If there are unallocated blocks available for the CE, one or more is reallocated as free blocks and used to replace the bad or defective block. When only one or no further unallocated blocks for the CE are available, the FTL places the CE in a read-only mode.

Abstract: Aspects of a storage device including a memory and a controller are provided which simplify controller management of logical and physical meta-dies and meta-blocks by allowing a logical meta-die to be mapped to multiple physical meta-dies. The memory includes first dies grouped in a first physical meta-die and second dies grouped in a second physical meta-die. The physical meta-dies each include physical meta-blocks. The controller maps a logical meta-die to the first physical meta-die and the second physical meta-die. The controller may also map logical meta-blocks of the logical meta-die to the physical meta-blocks. For instance, the controller may associate a first logical metablock of the logical meta-die to the first physical meta-die and a second logical metablock of the logical meta-die to the second physical meta-die. As a result, firmware complexity in managing meta-dies and meta-blocks may be reduced compared to one-to-one logical-to-physical meta-die mapping approaches.

Abstract: The present disclosure generally relates to methods and systems for allocating free blocks as decommissioned blocks to replace bad blocks. In certain embodiments, when there are insufficient free blocks in a free block list to replace a bad or defective block for a CE, an FTL scans blocks stored in an unallocated block repository. If there are unallocated blocks available for the CE, one or more is reallocated as free blocks and used to replace the bad or defective block. When only one or no further unallocated blocks for the CE are available, the FTL places the CE in a read-only mode.

Abstract: Aspects of a storage device including a memory and a controller are provided which simplify controller management of logical and physical meta-dies and meta-blocks by allowing a logical meta-die to be mapped to multiple physical meta-dies. The memory includes first dies grouped in a first physical meta-die and second dies grouped in a second physical meta-die. The physical meta-dies each include physical meta-blocks. The controller maps a logical meta-die to the first physical meta-die and the second physical meta-die. The controller may also map logical meta-blocks of the logical meta-die to the physical meta-blocks. For instance, the controller may associate a first logical metablock of the logical meta-die to the first physical meta-die and a second logical metablock of the logical meta-die to the second physical meta-die. As a result, firmware complexity in managing meta-dies and meta-blocks may be reduced compared to one-to-one logical-to-physical meta-die mapping approaches.

Abstract: The invention relates to new anti-hCD3 antibodies that, in contrast to prior art anti-CD3 antibodies, bind specifically to human CD3 at acidic pH, but do not significantly bind to human CD3 at neutral or physiological pH, methods to produce these antibodies and therapeutic uses of these antibodies. These antibodies are able to activate T cells at acidic pH while having significantly reduced activity at neutral or physiological pH.

Abstract: The present invention provides a method for preparing a modular scaffold that can bind to a target antigen and a method for engineering a bispecific functional agent consisting of an existing polypeptide binder fused at its C-terminus with said modular scaffold.

Abstract: The present invention provides a triple-mode antibody display system that simultaneously matures, displays and secretes an antibody to a target of interest. An antibody in vivo-matured and complexed with membrane anchored bait can be expressed on the surface of the host cell, while complexed with a soluble bait the antibody is secreted from the host cell. Methods of using the system for identifying binders that bind specifically to an antigen of interest are also provided. Polypeptides, polynucleotides and host cells useful for making the protein binder display system are also provided along with methods of use thereof.

Abstract: The present invention provides a method for preparing a modular scaffold that can bind to a target antigen and a method for engineering a bispecific functional agent consisting of an existing polypeptide binder fused at its C-terminus with said modular scaffold.

Abstract: The present invention provides a triple-mode antibody display system that simultaneously matures, displays and secretes an antibody to a target of interest. An antibody in vivo-matured and complexed with membrane anchored bait can be expressed on the surface of the host cell, while complexed with a soluble bait the antibody is secreted from the host cell. Methods of using the system for identifying binders that bind specifically to an antigen of interest are also provided.

Abstract: Provided, among other things, is a yeast cell comprising: (A) a recombinant DNA that constitutively or inducibly expresses a cytidine deaminase comprising sequence with about 90% sequence identity or more with a cytidine deaminase domain of (i) SEQ ID NO. 2 or SEQ ID NO. 4, or (ii) a chimera between the two starting with SEQ ID NO. 3 or SEQ ID NO. 4 sequence and having one transition to end in SEQ ID NO. 1 or SEQ ID NO. 2 sequence, or (iii) a chimera between the two starting with SEQ ID NO. 1 or SEQ ID NO. 2 sequence and having one transition to end in SEQ ID NO. 3 or SEQ ID NO. 4 sequence; and (B) a second recombinant DNA that constitutively or inducibly expresses a binding scaffold protein for presentation on the outer surface of the yeast, wherein the cytidine deaminase as expressed by the first recombinant DNA is effective to contribute to a mutagenic process for inducing mutations in the binding scaffold protein of the yeast cell.

Abstract: Writing servo wedge code to a disk is disclosed. A first selected burst demodulation window is determined. A final radial head position is computed based at least in part on the first selected burst demodulation window. Servo wedge code is written to a disk based at least in part on the final radial head position.

Abstract: Writing servo wedge code to a disk is disclosed. A wedge-to-wedge time interval is determined. At least until it is determined that a lock criterion is met: For each wedge-to-wedge time interval, a wedge frequency error is computed based on an adjustable clock. The clock is adjusted based on one or more of the wedge frequency errors. It is determined whether a lock criterion is met based on one or more of the wedge frequency errors. After the lock criterion is met, servo wedge code is written to the disk.

Abstract: System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement 400) with a plurality of switches (such as switch 405) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit 410). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit 505) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit 520) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.

Abstract: Methods for enhancing expression levels and secretion of heterologous fusion proteins in a host cell are disclosed.

Abstract: A method of operating a memory circuit having a plurality of blocks of memory cells (400-404) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells (400) is selected in response to a first address signal (RAY0). A row of memory cells (430-436) in the first block of memory cells is selected in response to a second address signal (RAX0). A first voltage is applied to a first power supply terminal (412) of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal (412) of another block of memory cells (402) of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.

Abstract: Systems and methods are provided for reducing leakage current and maintaining high performance in a static random access memory (SRAM). One embodiment discloses a memory array system operative to store data bits in individually addressable rows and columns. The memory array system comprises a plurality of memory blocks, each of the plurality of memory blocks having a plurality of memory rows and a row peripheral circuit operative to switch a memory block from a retention mode to an activation mode in response to an addressing of a memory row within the memory block.

Abstract: Methods for enhancing expression levels and secretion of heterologous fusion proteins in a host cell are disclosed.

Abstract: System and method for providing power to circuitry while avoiding a large transient current. A preferred embodiment comprises a distributed switch (such as switch arrangement 400) with a plurality of switches (such as switch 405) coupling a power supply to the circuitry. Each switch is individually controlled by a control signal and is turned on sequentially. Also coupled to each switch is a pre-driver circuit (such as pre-driver circuit 410). The pre-driver circuit comprises a potential adjust circuit (such as potential adjust circuit 505) that rapidly adjusts a voltage potential at the switch and a rate adjust circuit (such as the rate adjust circuit 520) that accelerates the power ramp-up across the switch once transient currents are no longer a concern. Adjusting the voltage potential so that the switch operates in a saturation mode increases an effective capacitance across the switch and thereby retarding the power ramp-up across the switch.