Abstract: A high speed signal driving scheme is disclosed which reduces timing delays associated with a signal line by limiting the voltage transition on the signal line from its precharged voltage.

Abstract: A self latching input buffer is disclosed which includes an address input buffer which is responsive to a first clock signal so as to produce an output signal. Data in the input buffer is latched in connection with the receipt of a second clock signal which is produced by a detector which is responsive to the output signal.

Abstract: A BiCMOS static random access memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column in the memory array is associated with a first stage sense amplifier, and the first stage sense amplifiers are arranged in groups, with each group connected in wired-OR fashion to a pair of local data lines. The column address is used to select one of the first stage sense amplifiers for sensing the state of the memory cell in the selected column. One second stage sense amplifier is associated with each group of first stage sense amplifiers, and the second stage sense amplifier associated with the group containing the selected first stage sense amplifier is selected, according to the most significant bits of the column address. The second stage sense amplifiers are connected to a data-out bus in wired-OR fashion, with the output of the selected second stage sense amplifier driving the data-out bus.

Abstract: A BiCMOS static random access memory is disclosed, where the sense amplifiers each consist of a pair of bipolar transistors connected in emitter-coupled fashion. A pair of current sources, such as MOS transistors, are connected between the bases of said bipolar transistors and ground, to provide additional pull-down current for the bit lines. This additional pull-down current reduces the differential bit line voltage, improving the speed at which subsequent reads may be performed. Another embodiment uses a dummy column as a detection circuit, with the output of the dummy column controlling an operational amplifier, so that the operational amplifier may bias the current source pair to control the pull-down current, and thus the differential bit line voltage. Another embodiment controls the current source pair responsive to the row address, so that the effects of series bit line resistance may be taken into account in establishing the desired pull-down current.

Abstract: The described embodiments of the present invention provide a structure and method for easily incorporating a high voltage lateral bipolar transistor in an integrated circuit. A buried base contact is formed and the base itself is formed of a well region in the integrated circuit. An oppositely doped well region is formed surrounding the collector region in the lateral PNP transistor. This collector well is formed of the opposite conductivity type of the base well. Contact to the collector and a heavily doped emitter are then formed in the collector well and base well, respectively. The more lightly doped collector well provides a thick depletion region between the collector and base and thus provides higher voltage operation. The positioning of the base/collector junction to the collector well at base well junction also reduces the spacing between the collector and the emitter.

Abstract: A threshold control BiCMOS TTL input buffer is disclosed which substantially eliminates input trip point variation across power supply, process, and temperature and additionally minimizes buffer power dissipation.

Abstract: A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resitive circuitry which allow bootstrapped voltages.

Abstract: A sense amplifier (10) has P channel transistors (38,48) connected between first and second nodes (34,44) of the sense amplifier and respective bitlines (12,14). The gates (42,52) of the P channel transistors (38,48) are connected to ground. As the voltage at one of the nodes (34 or 44) approaches ground voltage during the sensing operation, the bitline (12 or 14) is effectively disconnected from the sense amplifier (10) thereby increasing sensing speed while reducing noise between the bitline and the node.

Abstract: A BiCMOS current source reference network which eliminates the impact of d.c. power supply voltage drops on the operation of ECL circuits is described. This invention is essential for implementing ECL design techniques in VLSI BiCMOS circuits. Using the current source network, reference voltages are generated locally so that the ECL voltage references are correctly referenced to the local power supply potentials. A power supply insensitive band-gap reference generator is used to generate precision on-chip voltage references and current sources. The band-gap circuit uses both MOS and bipolar transistors and is much simpler than a similar using bipolar-only circuitry.

Abstract: A sense amplifier (10) is provided for with use with a static random access memory. Cascode preamplifier transistors (20a, 20b) convert the complementary currents appearing on bitlines (14a, 14b) coupled to the complementary outputs BIT and BIT of a memory cell (12). The currents are converted into differential voltages and amplified into emitter coupled logic compatible voltages which are output from sense amplifier (10) on DATA line (30a) and DATA line (30b). In a preferred embodiment, a first feedback loop is provided from DATA line (30b) to preamplifying transistor (20a) and a second feedback loop is provided from DATA line (30a) to preamplifier transistor (20b).

Abstract: A static random access memory is disclosed which has a first power supply terminal for receiving a power supply voltage for powering the periphery of the device and the array, and which has a second power supply terminal for receiving a power supply voltage for powering the array only. A diode may be connected between the two terminals to effect the biasing of the array from the first power supply terminal but not from the second power supply terminal. The memory may be incorporated into a system which has a power fail detector for controlling a switch, so that the battery is connected to the second power supply terminal when the main power supply has failed, but so that the main power supply is connected thereto when operable.

Abstract: A sensing and decoding scheme layout for a memory device comprising an array made up of columns and rows of memory cells is disclosed wherein sense amplifiers and pairs of memory cell columns are positioned so as to collectively fit within the pitches of the memory cells of the memory cell column pairs and where the sense amplifiers are connected in a one-to-one correspondence with columns of the memory cells.

Abstract: An output driver circuit for reducing output terminal ringing in integrated circuits has a plurality of pull-down transistors each having first, second and third terminals. A plurality of voltage setting devices each are connected in series to the second terminal of one of the pull-down transistors. An input is connected to the common third terminals of the plurality of pull-down transistors, and an output pull-up circuit is connected between the output of the circuit and the first terminals of the plurality of pull-down transistors. Multiple output driver circuits, each having an input delayed with respect to the others, can be connected together with a common output.

Abstract: A bipolar-CMOS static random access memory device includes a plurality of static random access memory cells arranged in columns and rows, complementary pairs of bit lines coupled to the cells in each row, word lines coupled to the cells in each row of the cells and a plurality of sense amplifiers with a separate sense amplifier coupled to each pair of the complementary bit lines. The memory device further includes bipolar pull-up transistors for each of the bit lines, with the collectors of the pull-up transistors coupled to a power supply node and the emitters coupled to the bit lines. Circuitry is provided which biases the bases of the pull-up transistors so that the pull-up transistors are on during a read operation, and so that the pull-up transistor associated with the low side bit line during a write operation is turned off. In addition, the pull-up transistors for both bit lines are biased to the on-state in a write operation for those columns which are not selected.

Abstract: A BiCMOS static random access memory is disclosed, where the sense amplifiers each consist of a pair of bipolar transistors connected in emitter-coupled fashion. A pair of current sources, such as MOS transistors, are connected between the bases of said bipolar transistors and ground, to provide additional pull-down current for the bit lines. This additional pull-down current reduces the differential bit line voltage, improving the speed at which subsequent reads may be performed. Another embodiment uses a dummy column as a detection circuit, with the output of the dummy column controlling an operational amplifier, so that the operational amplifier may bias the current source pair to control the pull-down current, and thus the differential bit line voltage. Another embodiment controls the current source pair responsive to the row address, so that the effects of series bit line resistance may be taken into account in establishing the desired pull-down current.

Abstract: A threshold control BICMOS TTL input buffer is disclosed which substantially eliminates input trip point variation across power supply, process, and temperature and additionally minimizes buffer power dissipation.

Abstract: A driver circuit is provided which offers decreased input loading, increased output loading, and a high voltage output level corresponding to a logic-1. These results are achieved through the use of pull-up transistors and capacitive and resitive circuitry which allow bootstrapped voltages.

Abstract: A BiCMOS static random access memory (SRAM) device is disclosed. The SRAM has an individual sense amplifier for each column therein, with bipolar pull-up transistors at the end of the bit lines opposite the sense amplifier. A pull-up control circuit which responds to the input data bus is provided for controlling the bias of the bases of the pull-up transistors so that, during a read cycle, the base of the pull-up device associated with the low side bit line is biased to a voltage which is lower than that to which the base of the pull-up device will be biased for a read; as a result, the time at which the bit line voltages cross-over for a read of an opposite data state is reduced. The pull-up control circuit further provides a low pass filter, for reducing the effects of power supply noise on the bit line differential voltage.

Abstract: A BiCMOS static random access memory (SRAM) is disclosed, which has first and second stage sense amplifiers. Each column in the memory array is associated with a first stage sense amplifier, and the first stage sense amplifiers are arranged in groups, with each group connected in wired-AND fashion to a pair of local data lines. The column address is used to select one of the first stage sense amplifiers for sensing the state of the memory cell in the selected column. One second stage sense amplifier is associated with each group of first stage sense amplifiers, and the second stage sense amplifier associated with the group containing the selected first stage sense amplifier is selected, according to the most significant bits of the column address. The second stage sense amplifiers are connected to a data-out bus in wired-OR fashion, with the output of the selected second stage sense amplifier driving the data-out bus.

Abstract: A pass circuit (54) passes a boot signal through a first transistor (60) when the pass circuit (54) is selected by a select signal (106). A second transistor (100) is precharged prior to receiving the select signal (106). In response to the select signal (106), a high voltage is passed to the first transistor (60) and the voltage at the gate of the second transistor (100) is pulled above a high voltage. After a delay period, another transistor (88) conducts between the gate of the second transistor (100) and V.sub.cc, to discharge the gate voltage. With both the source and gate of the second transistor (100) at a high voltage, the second transistor (100) is put in a non-conducting state. As the boot signal passes through the first transistor (60), the gate voltage of the first transistor (60) is increased above a high voltage, but the voltage at the gate of the second transistor (100) is maintained at V.sub.CC, thus preventing junction breakdown.