Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to an erase gate line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the erase gate line in response to changes in a voltage of the source line.

Abstract: In one example, a system comprises an analog neural memory array comprising a plurality of non-volatile memory cells arranged into rows and columns; and a voltage generator to provide a voltage to one or more rows of the analog neural memory array, the voltage generator comprising a voltage ladder to generate a plurality of voltages according to a logarithmic formula.

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.

Abstract: Numerous examples are disclosed of programming multiple rows in an array in an artificial neural network as part of a single programming operation. In one example, a method comprises ramping up an output of a high voltage generator to a first voltage level; while maintaining the output of the high voltage generator at the first voltage level, programming a plurality of words of K rows of memory cells in an array of memory cells using the output of the high voltage generator, where K>1; and after the programming, ramping down the output of the high voltage generator to a second voltage level.

Abstract: Numerous examples are disclosed of output circuitry and associated methods in an artificial neural network. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns, an output block to convert current from columns of the array into a first digital output during a first time period and a second digital output during a second time period, a first output register to store the first digital output during the first time period and to output the stored first digital output during the second time period, and a second output register to store the second digital output during the second time period and to output the stored second digital output during a third time period.

Abstract: Numerous examples are disclosed of input circuitry and associated methods in an artificial neural network. In one example, a system comprises a plurality of address decoders to receive an address and output a plurality of row enabling signals in response to the address; a first plurality of registers to store, sequentially, activation data in response to the plurality of row enabling signals; and a second plurality of registers to store, in parallel, activation data received from the first plurality of registers.

Abstract: In one example, a non-volatile memory system comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain of each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to a word line of the array during an operation, wherein the adaptive bias decoder adjusts the voltage provided to the word line in response to changes in a voltage of the source line.

Abstract: Numerous examples are disclosed of verification circuitry and associated methods in an artificial neural network. In one example, a system comprises a vector-by-matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns, the non-volatile memory cells respectively capable of storing one of N possible levels corresponding to one of N possible currents, and a plurality of output blocks to receive current from respective columns of the vector-by-matrix multiplication array and generate voltages during a verify operation of the vector-by-matrix multiplication and generate digital outputs during a read operation of the vector-by-matrix multiplication.

Abstract: In one example, a system comprises an array comprising selected memory cells; an input block configured to apply, to each selected memory cell, a series of input signals to a terminal of the selected memory cell in response to a series of input bits; and an output block for generating an output of the selected memory cells, the output block comprising an analog-to-digital converter to convert current from the selected memory cells into a digital value, a shifter, an adder, and a register; wherein the shifter, adder, and register are configured to receive a series of digital values in response to the series of input bits, shift each digital value in the series of digital values based on a bit location of an input bit within the series of input bits, and add results of the shift operations to generate an output indicating values stored in the selected memory cells.

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.

Abstract: In one example, a system comprises a neural network array of non-volatile memory cells arranged in rows and columns; and a logical cell comprising a first plurality of non-volatile memory cells in a first row of the array and a second plurality of non-volatile memory cells in a second row adjacent to the first row; wherein the first plurality of non-volatile memory cells and the second plurality of non-volatile memory cells are configured as one or more coarse cells and one or more fine cells.

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, an analog neural memory system comprises an array of non-volatile memory cells arranged into rows and columns, each non-volatile memory cell comprising a word line terminal, a bit line terminal, and an erase gate terminal; a plurality of word lines, each word line coupled to word line terminals of a row of non-volatile memory cells; a plurality of bit lines, each bit line coupled to bit line terminals of a column of non-volatile memory cells; and a plurality of erase gate enable transistors, each erase gate enable transistor coupled to erase gate terminals of a word of non-volatile memory cells.

Abstract: The invention relates to a method and a system for allocating a power request PREQ to a plurality of batteries connected in parallel in an electrical energy storage system. According to the invention, the allocation system comprises a global control system that can determine a combination of batteries from said plurality of batteries, which is optimized to respond to the power request using the highest possible number of batteries, and allocate a power level to each of the batteries of said optimized combination.

Abstract: A method detects defects in an electrical power storage system including at least one battery. The method includes applying an instruction for charging or discharging the battery. The method also includes measuring the current passing through the battery during application of the instruction and calculating m×n mean errors (eTj(tij))1?j?m, 1?i?n between the measured current and the theoretical current of the instruction in m×n time intervals ([tij, tij+Tj])1?j?m, 1?i?n, respectively. The method also includes calculating, for each j between 1 and m, ej=max(eTj (tij)), where i=1, . . . , n. Lastly, the method includes incrementing a counter Cj if ej completely or partially exceeds a predetermined threshold. A defect is detected if Cj exceeds a predetermined threshold.

Abstract: An electrical power supply system includes a battery of cells, the battery including an ammeter configured to measure battery current flowing through the battery, and at least one voltage sensor configured to measure voltage at terminals of a cell. An electronic control unit is configured to deliver a maximum permissible electrical power setpoint. The control unit is configured to calculate a maximum permissible electrical power associated with a cell by taking the minimum of at least two values, including a first electrical power and a second electrical power.

Abstract: A system of electric batteries includes a plurality of batteries (HVB1, HVB2, HVB3) connected to each other by two polarities. Each battery has at least two relays (RN, RP, RA) for the connecting of poles of the battery to the two polarities. The system includes a secondary power supply to provide an activation energy to the relays. The system includes means of supervision to control the relays (RN, RP, RA) in a staggered manner so that each activation of a relay follows a previous activation by at least a predetermined time period (DT).

Abstract: The invention relates to a method and a system for allocating a power request PREQ to a plurality of batteries connected in parallel in an electrical energy storage system. According to the invention, the allocation system comprises a global control system that can determine a combination of batteries from said plurality of batteries, which is optimized to respond to the power request using the highest possible number of batteries, and allocate a power level to each of the batteries of said optimized combination.

Abstract: A method detects defects in an electrical power storage system including at least one battery. The method includes applying an instruction for charging or discharging the battery. The method also includes measuring the current passing through the battery during application of the instruction and calculating m×n mean errors (eTj(tij))1?j?m, 1?i?n between the measured current and the theoretical current of the instruction in m×n time intervals ([tij, tij+Tj])1?j?m, 1?i?n, respectively. The method also includes calculating, for each j between 1 and m, ej=max(eTj (tij)), where i=1, . . . , n. Lastly, the method includes incrementing a counter Cj if ej completely or partially exceeds a predetermined threshold. A defect is detected if Cj exceeds a predetermined threshold.

Abstract: A system of electric batteries includes a plurality of batteries (HVB1, HVB2, HVB3) connected to each other by two polarities. Each battery has at least two relays (RN, RP, RA) for the connecting of poles of the battery to the two polarities. The system includes a secondary power supply to provide an activation energy to the relays. The system includes means of supervision to control the relays (RN, RP, RA) in a staggered manner so that each activation of a relay follows a previous activation by at least a predetermined time period (DT).

Abstract: The invention relates to a voltage converter (100), including: a plurality of two-way conversion cells (303), each cell comprising a primary circuit (307, Wp), and a secondary circuit (308, Ws) that is insulated from the primary circuit, wherein each circuit can be separately activated in order to supply an output voltage from the converter; and at least one control circuit (306) configured to, in a first operating mode, control the activated cells in order to transfer electrical energy from the primary circuit to the secondary circuit, and control the inactivated cells in order to transfer electrical energy from the secondary circuit to the primary circuit.