Patents by Inventor Himanshu Goel
Himanshu Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9632958Abstract: A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core.Type: GrantFiled: July 6, 2014Date of Patent: April 25, 2017Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Yashpal Dutta, Himanshu Goel, Varun Sethi
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Publication number: 20160004654Abstract: A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core.Type: ApplicationFiled: July 6, 2014Publication date: January 7, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Yashpal Dutta, Himanshu Goel, Varun Sethi
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Publication number: 20150288366Abstract: An integrated circuit (IC) includes multiple circuit modules that have specific clocking requirements, multiple clock sources (e.g., PLLs, duty cycle re-shaper, etc.), and at least one clock input port. The clock sources have specific clock source specifications, and the circuit modules have specific clocking requirements. The clock sources are selected based on an identification of the most common clocking requirements, and then placed at routing distances measured from the input port that are less than corresponding predetermined maximum routing distances such that the clocking requirements of the circuit modules are met. The IC thus generates clock signals internally, rather than externally.Type: ApplicationFiled: April 8, 2014Publication date: October 8, 2015Applicant: Freescale Semiconductor, Inc.Inventors: Amit Aggarwal, Himanshu Goel, Ashish Malhotra, Ankit Pal
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Patent number: 9148155Abstract: An integrated circuit (IC) includes multiple circuit modules that have specific clocking requirements, multiple clock sources (e.g., PLLs, duty cycle re-shaper, etc.), and at least one clock input port. The clock sources have specific clock source specifications, and the circuit modules have specific clocking requirements. The clock sources are selected based on an identification of the most common clocking requirements, and then placed at routing distances measured from the input port that are less than corresponding predetermined maximum routing distances such that the clocking requirements of the circuit modules are met. The IC thus generates clock signals internally, rather than externally.Type: GrantFiled: April 8, 2014Date of Patent: September 29, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Amit Aggarwal, Himanshu Goel, Ashish Malhotra, Ankit Pal
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Patent number: 8689068Abstract: An integrated circuit (IC) having a low leakage current mode of operation has a number of modules for running respective applications. The modules have respective cells and respective test scan chain elements. The IC also has a controller for configuring an active module to operate in a functional mode and a selected inactive module to operate in a low leakage current mode. Configuring the selected inactive module to operate in low leakage current mode includes enabling scan mode of the selected inactive module, and applying a low leakage vector of input signals from the controller to the cells of the inactive module using the scan chain. Functional data outputs of the inactive module are disabled during low leakage current mode. In the meantime, the active modules continue to operate in the functional mode.Type: GrantFiled: November 28, 2011Date of Patent: April 1, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Siddhartha Jain, Himanshu Goel, Himanshu Kukreja
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Publication number: 20130139013Abstract: An integrated circuit (IC) having a low leakage current mode of operation has a number of modules for running respective applications. The modules have respective cells and respective test scan chain elements. The IC also has a controller for configuring an active module to operate in a functional mode and a selected inactive module to operate in a low leakage current mode. Configuring the selected inactive module to operate in low leakage current mode includes enabling scan mode of the selected inactive module, and applying a low leakage vector of input signals from the controller to the cells of the inactive module using the scan chain. Functional data outputs of the inactive module are disabled during low leakage current mode. In the meantime, the active modules continue to operate in the functional mode.Type: ApplicationFiled: November 28, 2011Publication date: May 30, 2013Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Siddhartha JAIN, Himanshu GOEL, Himanshu KUKREJA
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Patent number: 7657854Abstract: A method and system for designing a test circuit in a System on Chip (SOC) includes identifying the test design constraints of the test circuit. The SOC is partitioned logically into a first set of logic blocks and a second set of logic blocks. A first set of scan chains is inserted in the first set of logic blocks, and a second set of scan chains is inserted in the second set of logic blocks, based on the test design constraints. Bypass circuits are inserted in the paths of the second set of scan chains, which are capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC.Type: GrantFiled: October 3, 2007Date of Patent: February 2, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Himanshu Goel, Amit Sharma
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Publication number: 20080127021Abstract: A method and system for designing a test circuit in a System on Chip (SOC) includes identifying the test design constraints of the test circuit. The SOC is partitioned logically into a first set of logic blocks and a second set of logic blocks. A first set of scan chains is inserted in the first set of logic blocks, and a second set of scan chains is inserted in the second set of logic blocks, based on the test design constraints. Bypass circuits are inserted in the paths of the second set of scan chains, which are capable of bypassing at least one logic block of the second set of logic blocks during testing of the SOC.Type: ApplicationFiled: October 3, 2007Publication date: May 29, 2008Applicant: FREESCALE SEMICONDUCTOR, INCInventors: Himanshu Goel, Amit Sharma
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Publication number: 20050144415Abstract: An apparatus and a system, as well as a method and article, may operate to allocate one or more links from a plurality of memory locations included in a memory segment of a memory to a port at substantially one time.Type: ApplicationFiled: December 30, 2003Publication date: June 30, 2005Inventors: Sachin Doshi, Himanshu Goel
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Publication number: 20050010683Abstract: A method, apparatus, and system for maintaining an uncorrupted table.Type: ApplicationFiled: June 30, 2003Publication date: January 13, 2005Inventors: Prabhanjan Moleyar, Vishram Sarurkar, Himanshu Goel, Ajith Prasad, Muralidharan Chilukoor