Patents by Inventor Hiroaki Fujimoto

Hiroaki Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060208349
    Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip.
    Type: Application
    Filed: March 30, 2006
    Publication date: September 21, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toshiyuki Fukuda, Hiroaki Fujimoto, Mutsuo Tsuji, Takashi Yui, Yoshiaki Takeoka
  • Patent number: 7087455
    Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: August 8, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Fukuda, Hiroaki Fujimoto, Mutsuo Tsuji, Takashi Yui, Yoshiaki Takeoka
  • Patent number: 7078818
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: July 18, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Publication number: 20060079023
    Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip.
    Type: Application
    Filed: November 18, 2005
    Publication date: April 13, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toshiyuki Fukuda, Hiroaki Fujimoto, Mutsuo Tsuji, Takashi Yui, Yoshiaki Takeoka
  • Publication number: 20050194676
    Abstract: There are provided a lead frame including a plurality of first external terminal portions 5 provided on a plane, inner lead portions 6 formed of back surfaces of the respective first external terminal portions and arranged so as to surround a region inside the inner lead portions, and second external terminal portions 7 formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor element 2 flip-chip bonded to the inner lead portions via bumps 3; and an encapsulating resin 4 encapsulating surroundings of the semiconductor element and the inner lead portions. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin.
    Type: Application
    Filed: March 3, 2005
    Publication date: September 8, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshiyuki Fukuda, Masanori Minamio, Hiroaki Fujimoto, Ryuichi Sahara, Kenichi Itou
  • Patent number: 6924173
    Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.
    Type: Grant
    Filed: March 14, 2003
    Date of Patent: August 2, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
  • Publication number: 20050133892
    Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.
    Type: Application
    Filed: January 26, 2005
    Publication date: June 23, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Tsuyoshi Hamatani, Toru Nomura
  • Patent number: 6815255
    Abstract: A semiconductor device includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The first and the second semiconductor chips are integrated so that the first and second main surfaces are opposed to one another and the first and second electrodes are electrically connected. The second semiconductor chip is polished from the opposite side of the second main surface so that the second semiconductor chip has a thickness smaller than the thickness of the first semiconductor chip.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: November 9, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukiko Nakaoka, Kazuhiko Matsumura, Hideyuki Kaneko, Koichi Nagao, Hiroaki Fujimoto
  • Patent number: 6777796
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: August 17, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Publication number: 20040145040
    Abstract: A semiconductor device and a manufacturing method for the same are provided wherein the reliability of connections of fine metal wires connecting a second semiconductor chip to a wiring board can be improved in the case wherein the second semiconductor chip, which is located above the lower, first semiconductor chip, is significantly larger than the first semiconductor chip in a configuration wherein two semiconductor chips are stacked and mounted on a wiring board. In this semiconductor device the rear surface of the first semiconductor chip and the rear surface of the second semiconductor chip are adhered to each other by means of adhesive and the side of the adhesive is inclined from the edge portions of the first semiconductor chip toward the portions of the second semiconductor chip extending from the side of the first semiconductor chip.
    Type: Application
    Filed: August 8, 2003
    Publication date: July 29, 2004
    Inventors: Toshiyuki Fukuda, Hiroaki Fujimoto, Mutsuo Tsuji, Takashi Yui, Yoshiaki Takeoka
  • Patent number: 6764879
    Abstract: A semiconductor wafer of the present invention includes: a plurality of semiconductor chip areas each of which is to be a semiconductor chip; and a cut-off area for separating the plurality of semiconductor chip areas from one another so as to obtain the semiconductor chips, wherein: an integrated circuit and an electrode pad connected to the integrated circuit are provided in each of the semiconductor chip areas; and a probe pad connected to the electrode pad is provided in the cut-off area.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: July 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koichi Nagao, Hiroaki Fujimoto
  • Patent number: 6713880
    Abstract: A semiconductor device includes a semiconductor chip, an insulating layer formed on a region excluding the plurality of electrode pads on the principal surface of the semiconductor chip, a plurality of contact pads arranged on the insulating layer, a wiring layer electrically connected to at least one of the plurality of electrode pads and electrically connected to at least one of the plurality of contact pads, thereby establishing rewiring connection, an insulative resin layer formed on a region excluding the plurality of contact pads on the principal surface of the semiconductor chip, a protruded electrode provided on each of the plurality of contact pads, and an underfill material layer provided on the insulative resin layer in such a manner that the top of the protruded electrode is exposed.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: March 30, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryuichi Sahara, Hiroaki Fujimoto
  • Patent number: 6707143
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Patent number: 6693347
    Abstract: A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: February 17, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Yoshinobu Kunitomo, Takashi Yui
  • Publication number: 20040029314
    Abstract: A semiconductor device includes a first semiconductor chip provided with a first electrode on a first main surface and a second semiconductor chip provided with a second electrode on a second main surface. The first and the second semiconductor chips are integrated so that the first and second main surfaces are opposed to one another and the first and second electrodes are electrically connected. The second semiconductor chip is polished from the opposite side of the second main surface so that the second semiconductor chip has a thickness smaller than the thickness of the first semiconductor chip.
    Type: Application
    Filed: July 18, 2003
    Publication date: February 12, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukiko Nakaoka, Kazuhiko Matsumura, Hideyuki Kaneko, Koichi Nagao, Hiroaki Fujimoto
  • Patent number: 6680220
    Abstract: A semiconductor device includes: a wiring substrate; a wiring electrode; a semiconductor chip; a connecting member; a resin encapsulant; and a mark member. The wiring electrode is formed on the wiring substrate. The semiconductor chip is mounted on the wiring substrate. An electrode pad formed on the semiconductor chip and the wiring electrode are electrically connected to each other with the connecting member. The semiconductor chip, the wiring electrode, and the connecting member, for example, are molded with the resin encapsulant on the upper surface of the wiring substrate. The mark member is embedded in the upper surface of the resin encapsulant. The mark member, which is transferred from a transfer sheet in a single process step, is highly visible and can be formed efficiently.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: January 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Hiroaki Fujimoto, Ryuichi Sahara, Toshiyuki Fukuda, Toru Nomura
  • Patent number: 6680524
    Abstract: A semiconductor device includes: a wiring substrate; a wiring electrode; a semiconductor chip; a connecting member; and a resin encapsulant. The wiring electrode is formed on the wiring substrate. The semiconductor chip is mounted on the wiring substrate and a second bottom face of the semiconductor chip is in contact with the wiring substrate. An electrode pad formed on the semiconductor chip and the wiring electrode are electrically connected to each other with the connecting member. The semiconductor chip, the wiring electrode, and the connecting member, for example, are molded with the resin encapsulant on the upper surface of the wiring substrate. A level difference exists between a first bottom face and the second bottom face of the semiconductor chip. The first and second bottom faces are respectively located at a peripheral portion and a central portion of the semiconductor chip. A part of the resin encapsulant is interposed between the first bottom face and the upper surface of the wiring substrate.
    Type: Grant
    Filed: October 24, 2001
    Date of Patent: January 20, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Hiroaki Fujimoto, Ryuichi Sahara, Toshiyuki Fukuda, Toru Nomura
  • Publication number: 20040006423
    Abstract: A movable object maneuver method wherein a destination point is set; wherein a thrust value is calculated in real time which minimizes or maximizes a performance index associated with one or more state variables and thrust required for a movable object to reach the destination point and which takes into account non-linear conditions inherent to the movable object; and wherein the movable object is moved based on the calculated thrust value.
    Type: Application
    Filed: May 20, 2003
    Publication date: January 8, 2004
    Applicants: KAWASAKI JUKOGYO KABUSHIKI KAISHA, KABUSHIKI KAISHA KAWASAKI ZOSEN
    Inventors: Hiroaki Fujimoto, Yukinobu Kohno, Masaaki Higashi, Masanori Hamamatsu, Kenichi Nakashima, Yasuo Saito, Hiroshi Ohnishi
  • Publication number: 20030194834
    Abstract: Disclosed is a semiconductor device 10 comprising a first semiconductor element 11 with an arrangement of first element electrodes 12, a second semiconductor element 13 with an arrangement of second element electrodes 14, a connection member 15 electrically connecting together a portion 12b of the first element electrodes 12 and the second element electrodes 14, an insulation layer 17 covering a major surface 11a of the first semiconductor element 11 and a backside surface 13b of the second semiconductor element 13, a wiring layer 22 formed on the insulation layer 17 and electrically connected to the first element electrode portion 12b exposed in an opening portion 21, and an external electrode 23 formed, as a portion of the wiring layer 22, on the insulation layer 17.
    Type: Application
    Filed: March 14, 2003
    Publication date: October 16, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Kazumi Watase, Hiroaki Fujimoto, Ryuichi Sahara, Nozomi Shimoishizaka, Takahiro Kumakawa, Kazuyuki Kaino, Yoshifumi Nakamura
  • Patent number: 6612272
    Abstract: Cooling arrangements that cool down fuel injectors exposed to the high temperature combustion in direct injected engines so that no heavy oil components deposit on nozzles of the fuel injectors. A bypass of water flow extends in the proximity of the boss where the fuel injector is inserted to expedite cooling of the fuel injector. A cavity extending toward the boss can replace the bypass or can be additionally provided. The fuel injector boss and a spark plug boss are connected with each other and make a wall that can obstruct water flow. Another bypass is provided to clear water away from a backwater formed at the wall. In case that some heavy oil components deposit on the injector nozzles for some reasons, a control system for controlling the fuel injection is allowed to adjust amounts of the fuel basically in response to the temperature of the injector nozzle.
    Type: Grant
    Filed: October 1, 2001
    Date of Patent: September 2, 2003
    Assignee: Yamaha Marine Kabushiki Kaisha
    Inventors: Masahiko Kato, Takayuki Sato, Hiroaki Fujimoto