Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate and memory transistors, each of which has a laminate formed by alternately laminating insulating films and conductive films on the semiconductor substrate, a silicon pillar going through the laminate, a tunnel insulating film arranged on the surface of the silicon pillar facing the laminate, a charge accumulating layer arranged on the surface of the tunnel insulating film facing the laminate, and a block insulating film arranged on the surface of the charge accumulating layer facing the laminate and in contact with the conductive film. During a data deletion operation, a voltage is applied on the conductive film so that the potential of the silicon pillar with respect to the conductive film decreases as the cross-sectional area of the silicon pillar decreases.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate and memory transistors, each of which has a laminate formed by alternately laminating insulating films and conductive films on the semiconductor substrate, a silicon pillar going through the laminate, a tunnel insulating film arranged on the surface of the silicon pillar facing the laminate, a charge accumulating layer arranged on the surface of the tunnel insulating film facing the laminate, and a block insulating film arranged on the surface of the charge accumulating layer facing the laminate and in contact with the conductive film. During a data deletion operation, a voltage is applied on the conductive film so that the potential of the silicon pillar with respect to the conductive film decreases as the cross-sectional area of the silicon pillar decreases.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first and second select gate transistors that are coupled to corresponding word lines, and a peripheral circuit erase verifying the NAND cell unit by turning on the first and second select gate transistors, applying a predetermined voltage level on the source line, making a voltage level applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the second select gate transistor larger than that applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the first select gate transistor, and verifying data erase of the memory cell transistors.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.

Abstract: A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first and second select gate transistors that are coupled to corresponding word lines, and a peripheral circuit erase verifying the NAND cell unit by turning on the first and second select gate transistors, applying a predetermined voltage level on the source line, making a voltage level applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the second select gate transistor larger than that applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the first select gate transistor, and verifying data erase of the memory cell transistors.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.

Abstract: A nonvolatile semiconductor storage device including a NAND cell unit having a first and a second select gate transistor, a plurality of memory cell transistors series connected between the first and second select gate transistors that are coupled to corresponding word lines, and a peripheral circuit erase verifying the NAND cell unit by turning on the first and second select gate transistors, applying a predetermined voltage level on the source line, detecting a voltage level of the bit line at once under a state where a voltage level applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the second select gate transistor is arranged higher than that applied on one or more of the word lines coupled to the memory cell transistors relatively closer to the first select gate transistor, and verifying data erase based on the detected voltage.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a plurality of first element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a first cell array region into a band shape, a plurality of second element isolation insulating films formed on a surface of the semiconductor substrate corresponding to a second cell array region into a band shape. Each first element isolation insulating film has a level from a surface of the semiconductor substrate, the first charge storage layer has a level from the surface of the semiconductor substrate, and each second element isolation insulating film has a level from the surface of the semiconductor substrate, the level of each first element isolation insulating film being lower than the level of the first charge storage layer and higher than the level of each second element isolation insulating film.

Abstract: A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.

Abstract: A semiconductor device includes a semiconductor substrate including a first region and a second region being adjacent to the first region; a floating gate electrode layer formed above the semiconductor substrate in the first region, the floating gate electrode layer including a first width; a dummy gate electrode layer formed above the semiconductor substrate in the second region, the dummy gate electrode layer including a second width being greater than the first width of the floating gate electrode layer; a first gate insulating film formed on the floating gate electrode layer, the first gate insulating film including a first thickness; a second gate insulating film formed on the dummy gate electrode layer, the second gate insulating film including a second thickness being greater than the first thickness of the first gate insulating film; and a control gate electrode layer formed on the first and the second gate insulating films.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cells.

Abstract: A nonvolatile semiconductor memory device having a plurality of electrically rewritable nonvolatile memory cells connected in series together includes a select gate transistor connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gets transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with the same bias voltage as that for the other memory cell.