Patents by Inventor Hiroaki Naito
Hiroaki Naito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180106175Abstract: The problem of the present invention is to provide an exhaust gas purification catalyst which can exhibit sufficient purification performance under a high Ga condition while having a resistance to stress such as high-temperature and poisonous substances. The present invention relates to an exhaust gas purification catalyst comprising two or more catalyst coating layers on a substrate, wherein a lower catalyst coating layer that is present lower with respect to an uppermost catalyst coating layer has a structure where a large number of voids are included and high-aspect-ratio pores having an aspect ratio of 5 or more account for a certain proportion or more of the whole volume of voids, thereby to improve gas diffusivity in the lower catalyst coating layer.Type: ApplicationFiled: March 24, 2016Publication date: April 19, 2018Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, CATALER CORPORATIONInventors: Hiromasa SUZUKI, Masahide MIURA, Yoshinori SAITO, Satoru KATOH, Toshitaka TANABE, Tetsuhiro HIRAO, Tatsuya OHASHI, Hiroaki NAITO, Hirotaka ORI, Michihiko TAKEUCHI, Keiichi NARITA
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Patent number: 9935115Abstract: A nonvolatile semiconductor storage device includes a memory string including a plurality of memory cells connected in series with each other, and a select gate transistor connected to a first end of the memory string. The film thickness of a first hard mask on a select gate electrode of the select gate transistor is greater than the film thickness of a second hard mask film on a control gate electrode of the memory cells. The level of an upper surface of a first side wall insulating film provided on a side surface of the select gate transistor is higher than the level of an upper surface of the first hard mask film. The level of an upper surface of a second side wall insulating film provided on a side surface of the memory cells is higher than the level of an upper surface of the second hard mask film.Type: GrantFiled: March 9, 2016Date of Patent: April 3, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventor: Hiroaki Naito
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Publication number: 20180071680Abstract: The present invention is directed to address the following problem: in an exhaust gas purification catalyst comprising a dual catalyst of a combination of a startup catalyst and an underfloor catalyst, reduction in the gas diffusivity of the startup catalyst results in reduction in the use efficiency of a catalytic active site, resulting in reduction in purification performance. The present invention relates to an exhaust gas purification catalyst comprising a dual catalyst of a combination of a startup catalyst having a catalyst coating where a large number of voids are included and an underfloor catalyst, wherein high-aspect-ratio pores having an aspect ratio of 5 or more account for a certain rate or more of the whole volume of the voids, to thereby enhance the purification performance of the catalyst.Type: ApplicationFiled: March 24, 2016Publication date: March 15, 2018Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, CATALER CORPORATIONInventors: Hiromasa SUZUKI, Masahide MIURA, Yoshinori SAITO, Satoru KATOH, Toshitaka TANABE, Tetsuhiro HIRAO, Tatsuya OHASHI, Hiroaki NAITO, Hirotaka ORI, Michihiko TAKEUCHI, Keiichi NARITA
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Publication number: 20170256554Abstract: According to one embodiment, a conductive layer is patterned based on a first mask pattern to form word lines extending in a cell array region in a row direction, a slit is formed in the conductive layer in a peripheral region to form first air gaps between the word lines, a first insulation film is formed on the conductive layer to cover the slit, the conductive layer is patterned based on a second mask pattern to form select gate lines extending in the cell array region in the row direction, and the conductive layer in the peripheral region is divided in a column direction.Type: ApplicationFiled: August 22, 2016Publication date: September 7, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroaki NAITO
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Patent number: 9666239Abstract: According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance.Type: GrantFiled: March 2, 2015Date of Patent: May 30, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Hiroaki Naito, Tatsuya Fukumura
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Publication number: 20170141118Abstract: A nonvolatile semiconductor storage device includes a memory string including a plurality of memory cells connected in series with each other, and a select gate transistor connected to a first end of the memory string. The film thickness of a first hard mask on a select gate electrode of the select gate transistor is greater than the film thickness of a second hard mask film on a control gate electrode of the memory cells. The level of an upper surface of a first side wall insulating film provided on a side surface of the select gate transistor is higher than the level of an upper surface of the first hard mask film. The level of an upper surface of a second side wall insulating film provided on a side surface of the memory cells is higher than the level of an upper surface of the second hard mask film.Type: ApplicationFiled: March 9, 2016Publication date: May 18, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroaki NAITO
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Patent number: 9653314Abstract: A semiconductor device according to the present embodiment includes a plurality of wires. A plurality of wire drawing pads are provided correspondingly to the wires and electrically connecting a plurality of contacts to the wires, respectively. First space portions widen toward a first direction from the wires to the wire drawing pads and are located between adjacent ones of the wire drawing pads in a connection region between the wires and the wire drawing pads. Second space portions are provided at edge portions of the wire drawing pads. Air gaps or insulating layers are provided in the first space portions and the second space portions.Type: GrantFiled: December 17, 2014Date of Patent: May 16, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Nagashima, Koichi Matsuno, Takashi Sugihara, Hiroaki Naito
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Publication number: 20160141297Abstract: In one embodiment, a semiconductor device includes a substrate, and first to fourth interconnects provided on the substrate to be adjacent to one another. The device includes a first pad portion connected with the first or second interconnect, and a second pad portion adjacent to the first pad portion in a first direction. The device includes a third pad portion connected with the third or fourth interconnect, and adjacent to one of the first and second pad portions in a second direction, and a fourth pad portion adjacent to the third pad portion in the first direction, and adjacent to the other of the first and second pad portions in the second direction. The device includes one or more interconnects insulated from the first to fourth interconnects and the first to fourth pad portions, and provided between the first and second interconnects and the third and fourth interconnects.Type: ApplicationFiled: March 9, 2015Publication date: May 19, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hiroaki NAITO, Satoshi Nagashima
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Publication number: 20160071792Abstract: A semiconductor device according to the present embodiment includes a plurality of wires. A plurality of wire drawing pads are provided correspondingly to the wires and electrically connecting a plurality of contacts to the wires, respectively. First space portions widen toward a first direction from the wires to the wire drawing pads and are located between adjacent ones of the wire drawing pads in a connection region between the wires and the wire drawing pads. Second space portions are provided at edge portions of the wire drawing pads. Air gaps or insulating layers are provided in the first space portions and the second space portions.Type: ApplicationFiled: December 17, 2014Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Satoshi Nagashima, Koichi Matsuno, Takashi Sugihara, Hiroaki Naito
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Publication number: 20160064399Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell region and a peripheral circuit region arranged on a semiconductor substrate. In the peripheral circuit region, a stacked body including a tunnel insulating film, a floating gate electrode film, an inter-electrode insulating film, and a control gate electrode film stacked in this order, a first insulating film and a second insulating film are stacked on the semiconductor substrate. The peripheral circuit region includes a contact region where the stacked body removed a film above the floating gate electrode film, the first insulating film and the second insulating film are stacked. The peripheral circuit region includes contact provided within a region where the contact region is formed, and one end of the contact is in the second insulating film, and the other end of the contact is in the floating gate electrode film.Type: ApplicationFiled: December 12, 2014Publication date: March 3, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Hiroaki NAITO, Tatsuya FUKUMURA
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Patent number: 9257570Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a plurality of first electrodes provided on the first insulating film, a second insulating film provided on a side surface of the first electrodes and on an upper surface of the first electrodes, and a second electrode insulated from the first electrodes by the second insulating film. The second electrode includes an interconnect portion provided on the second insulating film, and a downward-extending portion extending into a space between the first electrodes from the interconnect portion. A lower end portion of the downward-extending portion is not covered with the second insulating film.Type: GrantFiled: January 23, 2014Date of Patent: February 9, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Sato, Hiroaki Naito, Satoshi Nagashima
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Publication number: 20160035396Abstract: According to an embodiment, a semiconductor device includes a plurality of wiring patterns of wiring lines disposed in parallel in a line-and-space pattern in a predetermined pitch and extend in a first direction in a first region, first bending patterns that extend pairs of the wiring lines in a second in a second region adjacent to the first region, second bending patterns extend the pairs of wiring lines in opposite directions along the orientation of the first direction in the second region, and dummy patterns separated from the two second bending patterns at a predetermined distance.Type: ApplicationFiled: March 2, 2015Publication date: February 4, 2016Inventors: Hiroaki NAITO, Tatsuya FUKUMURA
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Publication number: 20150372079Abstract: According to an embodiment, a non-volatile semiconductor memory device includes plural gate electrodes in which a first insulating film, a charge storage layer, a second insulating film, and a control gate electrode layer are sequentially stacked on a semiconductor substrate, in which the control gate electrode layer includes a polysilicon layer that is formed on the second insulating film and a metal layer that is formed on the polysilicon layer, and a portion of the metal layer having the maximum width dimension is positioned above a lower end portion of the metal layer.Type: ApplicationFiled: February 17, 2015Publication date: December 24, 2015Inventors: Hiroaki NAITO, Tatsuya FUKUMURA
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Publication number: 20150069487Abstract: A semiconductor memory device according to an embodiment includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a plurality of first electrodes provided on the first insulating film, a second insulating film provided on a side surface of the first electrodes and on an upper surface of the first electrodes, and a second electrode insulated from the first electrodes by the second insulating film. The second electrode includes an interconnect portion provided on the second insulating film, and a downward-extending portion extending into a space between the first electrodes from the interconnect portion. A lower end portion of the downward-extending portion is not covered with the second insulating film.Type: ApplicationFiled: January 23, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyasu SATO, Hiroaki Naito, Satoshi Nagashima
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Patent number: 8647082Abstract: A fuel pump may include a motor section comprising a rotor and a stator. One of the rotor and the stator may have at least a pair of permanent magnet parts disposed along a first circumferential surface at an interval in a circumferential direction, and at least two magnetic material parts disposed between ends of adjacent permanent magnet parts. The other one of the rotor and the stator may have a first yoke disposed so as to face the permanent magnet parts, wherein a plurality of slots are formed on the first yoke at an interval in the circumferential direction. A surface facing the slots of the magnetic material parts may be shifted, in at least a partial range in the circumferential direction including a permanent magnet part side end where a polarity of a first circumferential surface side is a north pole, from the first circumferential surface in a direction along which a distance to the slots increases.Type: GrantFiled: November 15, 2010Date of Patent: February 11, 2014Assignee: Aisan Kogyo Kabushiki KaishaInventors: Hiroaki Naito, Kazumichi Hanai
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Patent number: 8288903Abstract: A stator of a rotary electric motor has core segments. All or some of the core segments have terminal mounting members for mounting terminals to which coils are connected. The terminal mounting member and the bobbin for each of the core segments are molded by resin and integrated with the corresponding core segment.Type: GrantFiled: July 22, 2010Date of Patent: October 16, 2012Assignee: Aisan Kogyo Kabushiki KaishaInventors: Tatsuhisa Matsuda, Futoshi Abe, Kazumichi Hanai, Hiroaki Naito, Atsushi Sugimoto, Fusatomo Miyake
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Publication number: 20110116955Abstract: A fuel pump may include a motor section comprising a rotor and a stator. One of the rotor and the stator may have at least a pair of permanent magnet parts disposed along a first circumferential surface at an interval in a circumferential direction, and at least two magnetic material parts disposed between ends of adjacent permanent magnet parts. The other one of the rotor and the stator may have a first yoke disposed so as to face the permanent magnet parts, wherein a plurality of slots are formed on the first yoke at an interval in the circumferential direction. A surface facing the slots of the magnetic material parts may be shifted, in at least a partial range in the circumferential direction including a permanent magnet part side end where a polarity of a first circumferential surface side is a north pole, from the first circumferential surface in a direction along which a distance to the slots increases.Type: ApplicationFiled: November 15, 2010Publication date: May 19, 2011Applicant: AISAN KOGYO KABUSHIKI KAISHAInventors: Hiroaki Naito, Kazumichi Hanai
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Publication number: 20110020154Abstract: A stator of a rotary electric motor has core segments. All or some of the core segments have terminal mounting members for mounting terminals to which coils are connected. The terminal mounting member and the bobbin for each of the core segments are molded by resin and integrated with the corresponding core segment.Type: ApplicationFiled: July 22, 2010Publication date: January 27, 2011Applicant: AISAN KOGYO KABUSHIKI KAISHAInventors: Tatsuhisa MATSUDA, Futoshi ABE, Kazumichi HANAI, Hiroaki NAITO, Atsushi SUGIMOTO, Fusatomo MIYAKE
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Publication number: 20050254936Abstract: A fuel pump 10 may be with a substantially disk-shaped impeller 20 and a casing 14 for housing the impeller 20 such that the impeller 20 can rotate. Permanent magnets 26 may be disposed in the impeller 20. A driving coil 40 may be disposed in the casing 14 at a location opposite the permanent magnets 26. The impeller 20 rotates when power is supplied to the driving coil 40. The fuel pump 10 may include a supporting device 42 for supporting the impeller. The supporting device 42 may be located in at least one location in an inner face of the casing 14, this inner face of the casing being located opposite an upper face, a lower face, and an outer peripheral face of the impeller 20. It is preferred that the supporting device 42 has a rolling element that makes rolling contact with the impeller 20.Type: ApplicationFiled: May 11, 2005Publication date: November 17, 2005Inventors: Masaharu Hayakawa, Hiroaki Naito
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Publication number: 20050074343Abstract: A motor, possibly for a pump, has a housing, a first member disposed within the housing and mounted on an inner wall of the housing, and a second member rotatably disposed within the housing and having a rotary shaft. A thrust bearing is mounted within the housing in order to support a first end of the rotary shaft in an axial direction of the rotary shaft. A core and coils wound around the core are provided on one of the first and second members. A set of magnets is provided on the other of the first and second members. The core and the set of magnets are positioned such that a magnetic force is produced in an area where a magnetic flux is generated between the core and the set of magnets. The magnetic force causes the second member to move toward the thrust bearing.Type: ApplicationFiled: October 4, 2004Publication date: April 7, 2005Inventor: Hiroaki Naito