Patents by Inventor Hiroaki Nakanishi

Hiroaki Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100320132
    Abstract: Disclosed herein is a suppressor using one ion-exchange tube which has an inner diameter close to that of a tube connected to a separation column and which is constituted by an ion-exchange membrane. The ion-exchange tube is folded or wound more than once in a plane into a sheet form to provide an ion-exchange tube sheet through which an eluate from a separation column flows. The ion-exchange tube sheet is accommodated in a container. The container provides a regenerant flow channel so that a regenerant is allowed to flow on both sides of the ion-exchange tube sheet.
    Type: Application
    Filed: February 21, 2008
    Publication date: December 23, 2010
    Inventors: Katsumasa Sakamoto, Yukio Oikawa, Shigeyoshi Horiike, Hiroaki Nakanishi
  • Patent number: 7782690
    Abstract: A semiconductor device includes plural switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device, and a nonvolatile memory connected to the plural switching transistors and configured to store data for determining ON and OFF of the plural switching transistors. When the semiconductor device is in operation, ON and OFF of the switching transistors are determined by the data.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: August 24, 2010
    Assignee: Ricoh Company, Ltd.
    Inventor: Hiroaki Nakanishi
  • Publication number: 20100206675
    Abstract: A ventilated disc rotor includes a hat portion at which the ventilated disc rotor is attached to a rotation shaft, a sliding portion formed in an annular shape and provided at a radially outer portion of the hat portion, the ventilated disc rotor being slidably held by an inner pad and an outer pad at the sliding portion so as to brake a rotation of the ventilated disc rotor and the sliding portion including an inner disc-shaped portion, an outer disc-shaped portion and a plurality of cooling fins, wherein the hat portion and the plurality of cooling fins are integrally made of a steel plate material, and the outer disc-shaped portion and the inner disc-shaped portion are formed by casting together with the plurality of cooling fins in such a way that the plurality of cooling fins integrally connects the inner disc-shaped portion to the outer disc-shaped portion.
    Type: Application
    Filed: February 16, 2010
    Publication date: August 19, 2010
    Applicant: ADVICS CO., LTD.
    Inventors: Hiroyoshi Miyake, Masatoshi Kano, Hiroaki Nakanishi, Masatoshi Watanabe
  • Publication number: 20100103739
    Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.
    Type: Application
    Filed: December 31, 2009
    Publication date: April 29, 2010
    Applicant: RICOH COMPANY, LTD.
    Inventors: Minoru FUKUDA, Hiroaki NAKANISHI, Kunio MATSUDAIRA, Masahiro MATSUO, Hirohisa ABE
  • Publication number: 20100101943
    Abstract: A radioactive fluoride anion concentrating device capable of concentrating 18F? ions speedily and efficiently. A flow cell (11) is composed of a metal plate electrode (21), an insulating sheet (23) and a carbon plate electrode (25) located so that the sides of electrodes may be opposed to each other with the insulating sheet (23) inserted between them. An example of the plate metal plate electrode (21) is obtained by forming a film of metallic material on an insulation plate, and an example of the insulating sheet (23) is a PDMS from which a groove being a channel (26) having a thickness of ?500 ?m is cut out. The thickness of the sheet is desirably about 100 ?m. The upper and lower sides of the flow cell (11) are fixed by fixing jigs (27) and (29).
    Type: Application
    Filed: March 26, 2007
    Publication date: April 29, 2010
    Inventors: Ren Iwata, Eiichi Ozeki, Hiroaki Nakanishi, Katsumasa Sakamoto, Ryo Yamahara
  • Publication number: 20100059689
    Abstract: Provided is an ionization emitter which can reduce a dead volume without deteriorating separating capacity. An ionization emitter (2) is provided with a tip (1) composed of a columnar or conical porous self-standing structure, and a channel for supplying a solution sample into the tip (1) from the base end side of the tip (1). The channel is formed by filling a pipe line with a packing, and the tip (1) is exposed from the pipe line of the channel. The packing and the porous self-standing structure constituting the tip (1) have an integrated structure composed of a same porous body formed at the same time.
    Type: Application
    Filed: January 7, 2008
    Publication date: March 11, 2010
    Inventors: Shigeyoshi Horiike, Hiroaki Nakanishi
  • Patent number: 7672172
    Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: March 2, 2010
    Assignee: Ricoh Company, Ltd.
    Inventors: Minoru Fukuda, Hiroaki Nakanishi, Kunio Matsudaira, Masahiro Matsuo, Hirohisa Abe
  • Publication number: 20090146731
    Abstract: A disclosed reference voltage generating circuit for generating a reference voltage includes MOSFETs connected in series or in parallel. At least one of the MOSFETs includes a control gate and a floating gate that is made hole-rich or discharged by ultraviolet irradiation, and the reference voltage generating circuit is configured to output the difference between threshold voltages of a pair of the MOSFETs as the reference voltage.
    Type: Application
    Filed: March 20, 2007
    Publication date: June 11, 2009
    Applicant: RICOH COMPANY, LTD
    Inventors: Masaaki Yoshida, Hiroaki Nakanishi
  • Publication number: 20090096793
    Abstract: An electronically implemented method for processing an image is disclosed, the method including: receiving an electronic command for creating a printable image from a vector image, the vector image including a first arc connected to a second arc; converting the first arc into a plurality of first line segments, including a first start point and a first end point, the first start point and first end point having a first center point which represents the center of the first arc; converting the second arc into a plurality of second line segments, including a second start point and a second end point, the second start point and second end point having a second center point which represents the center of the second arc; determining that the first end point and second start point are both located at a connection point; determining that the first center point, connection point, and the second center point are aligned in a linear relationship with respect to each other; and adding a connection point shape which exten
    Type: Application
    Filed: October 15, 2008
    Publication date: April 16, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Masahiko Hirasawa, Hiroaki Nakanishi
  • Publication number: 20090091984
    Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of other flash memory array is enable when the plural sector flash memory array is gained access.
    Type: Application
    Filed: December 12, 2008
    Publication date: April 9, 2009
    Applicant: RICOH COMPANY, LTD.
    Inventors: Minoru FUKUDA, Hiroaki Nakanishi, Kunio Matsudaira, Masahiro Matsuo, Hirohisa Abe
  • Publication number: 20090080274
    Abstract: A semiconductor device includes plural switching transistors configured to perform trimming for characteristic adjustment of the semiconductor device, and a nonvolatile memory connected to the plural switching transistors and configured to store data for determining ON and OFF of the plural switching transistors. When the semiconductor device is in operation, ON and OFF of the switching transistors are determined by the data.
    Type: Application
    Filed: September 19, 2008
    Publication date: March 26, 2009
    Inventor: Hiroaki Nakanishi
  • Patent number: 7483312
    Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: January 27, 2009
    Assignee: Ricoh Company, Ltd
    Inventors: Minoru Fukuda, Hiroaki Nakanishi, Kunio Matsudaira, Masahiro Matsuo, Hirohisa Abe
  • Patent number: 7335557
    Abstract: A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.
    Type: Grant
    Filed: July 20, 2005
    Date of Patent: February 26, 2008
    Assignee: Ricoh Company, Ltd.
    Inventors: Masaaki Yoshida, Hiroaki Nakanishi
  • Patent number: 7314797
    Abstract: A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon oxide film is formed on its surface. A gate oxide film for a non-volatile memory is formed on a P substrate between N type diffusion layers. The floating gate is formed on the inter-layer silicon oxide film, the field oxide film, and the gate oxide film for the non-volatile memory. Since a large coupling ratio between the control gate and the floating gate is available on the field oxide film, memory rewriting requires only a low voltage. Further, since the control gate is formed by a poly silicon film, both a positive voltage and a negative voltage can be applied to the control gate.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: January 1, 2008
    Assignee: Ricoh Company, Ltd.
    Inventors: Moriya Iwai, Masaaki Yoshida, Hiroaki Nakanishi
  • Patent number: 7035980
    Abstract: A data look-ahead control is provided to realize a high cache hit rate and improves responsiveness in an information processing system. In the data look-ahead control, when it is determined that the current input/output request is an access to a specific database that was the subject of a recent input/output request and whose I/O count exceeds a predetermined value, and it is also determined that a cache memory can be occupied to some extent and that there would be no impact on other input/output requests, data including one or more blocks (logical tracks) larger than a block that is the subject of the current I/O request are loaded to the cache memory.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: April 25, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Isamu Kurokawa, Hiroaki Nakanishi, Junichi Muto, Hisaharu Takeuchi, Masahiro Kawaguchi
  • Publication number: 20050275041
    Abstract: A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon oxide film is formed on its surface. A gate oxide film for a non-volatile memory is formed on a P substrate between N type diffusion layers. The floating gate is formed on the inter-layer silicon oxide film, the field oxide film, and the gate oxide film for the non-volatile memory. Since a large coupling ratio between the control gate and the floating gate is available on the field oxide film, memory rewriting requires only a low voltage. Further, since the control gate is formed by a poly silicon film, both a positive voltage and a negative voltage can be applied to the control gate.
    Type: Application
    Filed: August 18, 2005
    Publication date: December 15, 2005
    Inventors: Moriya Iwai, Masaaki Yoshida, Hiroaki Nakanishi
  • Publication number: 20050258473
    Abstract: A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.
    Type: Application
    Filed: July 20, 2005
    Publication date: November 24, 2005
    Inventors: Masaaki Yoshida, Hiroaki Nakanishi
  • Patent number: 6952035
    Abstract: A non-volatile memory semiconductor device includes a first insulation layer, two diffusion regions, a memory gate oxide layer, a first control gate, a second insulation layer, a floating gate of polysilicon, a third insulation layer and a second control gate. The first insulation layer is formed on a semiconductor substrate. The two diffusion regions are formed on a surface of the substrate. The memory gate oxide layer is formed over the two diffusion regions on the substrate. The first control gate including a diffusion region is formed on the surface of the substrate. The second insulation layer is formed on the first control gate. The floating gate of polysilicon is formed over the memory gate oxide layer, the first insulation layer, and the second insulation layer. The third insulation layer is formed on the floating gate. The second control gate is disposed on the floating gate.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: October 4, 2005
    Assignee: Ricoh Company, Ltd.
    Inventors: Masaaki Yoshida, Hiroaki Nakanishi
  • Patent number: 6949790
    Abstract: A semiconductor device is capable of being applied with both a positive and a negative voltage to its control gate, and writing to its memory requires a low voltage. A control gate is formed on a memory unit region of a field oxide film, and an inter-layer silicon oxide film is formed on its surface. A gate oxide film for a non-volatile memory is formed on a P substrate between N type diffusion layers. The floating gate is formed on the inter-layer silicon oxide film, the field oxide film, and the gate oxide film for the non-volatile memory. Since a large coupling ratio between the control gate and the floating gate is available on the field oxide film, memory rewriting requires only a low voltage. Further, since the control gate is formed by a poly silicon film, both a positive voltage and a negative voltage can be applied to the control gate.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: September 27, 2005
    Assignee: Ricoh Company, Ltd.
    Inventors: Moriya Iwai, Masaaki Yoshida, Hiroaki Nakanishi
  • Patent number: RE40917
    Abstract: The present invention is related to a composite flash memory device comprises a plural sector flash memory array which is divided to plural sector that is a minimum erasing unit of the flash memory device, a flash memory array storing control commands which control a total system of the composite flash memory device and/or the only composite flash memory device in and sharing I/O line of the plural sector flash memory array, the read operation of the flash memory array is enable when the plural sector flash memory array is gained access.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: September 15, 2009
    Assignee: Ricoh Company, Ltd.
    Inventors: Minoru Fukuda, Hiroaki Nakanishi, Kunio Matsudaira, Masahiro Matsuo, Hirohisa Abe