Patents by Inventor Hiroaki Nakanishi

Hiroaki Nakanishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4530050
    Abstract: A central processing unit for executing instructions of variable length in which an operand specifier for specifying the addressing mode of an operand is independent of an operation code for ascertaining the kind of an operation and the number of operands. Each operand specifier is formed of one or more data bytes, and has a stop bit flag indicating whether or not the particular operand specifier is the last operand specifier. By adding the stop bit flag, the operand specifier can be shared, and different processing can be executed with an identical operation code. In a case where, when operation code decoding means has provided an output indicative of the last operand, the stop bit flat is not detected in the corresponding operand specifier, the corresponding instruction is detected as an error.
    Type: Grant
    Filed: August 17, 1982
    Date of Patent: July 16, 1985
    Assignees: Hitachi, Ltd., Hitachi Engineering Co., Ltd.
    Inventors: Yasushi Fukunaga, Tadaaki Bandoh, Kotaro Hirasawa, Hidekazu Matsumoto, Jushi Ide, Takeshi Katoh, Hiroaki Nakanishi, Tetsuya Kawakami, Ryosei Hiraoka
  • Patent number: 4494188
    Abstract: An operating system (OS) is divided into units (OS processes) which are concurrently executable. When the processors concurrently request the execution of one OS process, data indicating that the requested OS process is in a ready state is loaded into a memory. The other processors repeatedly make an access to the data during the course of the execution of the user's task to check to see whether the ready-state OS process is present or not. A processor when detecting the ready-state OS process ceases the execution of the user's program and executes that OS process.
    Type: Grant
    Filed: April 5, 1982
    Date of Patent: January 15, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Keiichi Nakane, Toshiro Kamiuchi, Hiroaki Nakanishi
  • Patent number: 4491912
    Abstract: A data processing system having a first storage for storing therein microprograms; an address register for supplying an instruction address of a microprogram to be executed into said first storage; a stack unit having a stack area for storing therein a return address of the microprogram; a first control unit responsive to a microinstruction for instructing a microsubroutine call to store the return address of the microinstruction in the stack unit, and responsive to a microinstruction for instructing return from the microsubroutine to restore the return address of the microinstruction from said stack unit; a second control unit for monitoring an interrupt request; a second storage for saving therein the content of said stack unit; a status register having a field for indicating the acceptance of the interrupt request in the course of the execution of the microprogram, and a third control unit responsive to the detection of the interrupt request by the second control unit in the course of the execution of the
    Type: Grant
    Filed: March 16, 1982
    Date of Patent: January 1, 1985
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Kainaga, Kousuke Sakoda, Hiroaki Nakanishi
  • Patent number: 4486834
    Abstract: A multi-computer system having a dual common memory adapted to perform Read/Write operations by means of a plurality of computers. Each computer in the system consists of a central processing unit, a main memory and a dual memory access unit. The dual memory access unit is adapted to provide a status signal representative of whether the data from the common memory is correct or not and a maintenance signal representative of whether a maintenance operation is demanded. A memory access is made only to the common memory demanding the maintenance when the program run by the computer is a maintenance program, and only to the normal common memory during the usual operation.
    Type: Grant
    Filed: April 14, 1983
    Date of Patent: December 4, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiki Kobayashi, Hideo Maejima, Tadaaki Bandoh, Hiroaki Nakanishi
  • Patent number: 4468733
    Abstract: A multi-computer system includes a plurality of data processors and at least one I/O device which is commonly accessible by the data processors. A plurality of serial bus loops are configurated in hierarchy with interbus linkage devices disposed between adjacent layers of the hierarchy. The data processors are connected to a plurality of first layer serial bus loops and the I/O device which is commonly accessible by the data processors is connected to a second layer of serial bus loop. The interbus linkage devices control linkage among the plurality of serial bus loops and carry out routing control for a start command from the data processor to the I/O device, routing control for an interruption to report the end of I/O device operation, routing control for data transfer, routing control for a request interruption and exclusive use control of the shared I/O device.
    Type: Grant
    Filed: June 4, 1981
    Date of Patent: August 28, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Toshihisa Oka, Hiroaki Nakanishi, Ryoichi Takamatsu, Takayuki Morioka, Masakazu Okada, Hideyuki Hara, Hirokazu Kasashima