Patents by Inventor Hiroaki Ohkubo
Hiroaki Ohkubo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9846831Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the transmitter are provided in a single IC (Integrated Circuit) chip and are not overlapped with each other in planar view, and the transmitter includes a coil.Type: GrantFiled: March 24, 2016Date of Patent: December 19, 2017Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Hiroaki Ohkubo, Mitsuji Okada, Shigeharu Nakata, Shuuichi Kagawa
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Publication number: 20160203394Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit.Type: ApplicationFiled: March 24, 2016Publication date: July 14, 2016Inventors: Yasutaka Nakashiba, Hiroaki Ohkubo, Mitsuji Okada, Shigeharu Nakata, Shuuichi Kagawa
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Patent number: 9305253Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view.Type: GrantFiled: August 12, 2013Date of Patent: April 5, 2016Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Hiroaki Ohkubo, Mitsuji Okada, Shigeharu Nakata, Shuuichi Kagawa
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Patent number: 8810699Abstract: A solid state imaging device has a semiconductor substrate, a light receiving region provided on a surface layer on a first surface side of the semiconductor substrate, the light receiving region having a silicided surface, second impurity diffusion layer provided adjacent to the light receiving region on the surface layer on the first surface side of the semiconductor substrate, a gate insulating film provided adjacent to the second impurity diffusion layer on the first surface of the semiconductor substrate, a gate electrode provided on the gate insulating film, and a third impurity diffusion layer provided on an opposite side to the second impurity diffusion layer, with the gate insulating film and the gate electrode sandwiched.Type: GrantFiled: February 2, 2012Date of Patent: August 19, 2014Assignee: Renesas Electronics CorporationInventors: Hiroaki Ohkubo, Yasutaka Nakashiba
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Publication number: 20130327838Abstract: A memory card includes a memory that stores data, a driver that transmits the data received from the memory, and at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit. The driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped with each other in a planar view.Type: ApplicationFiled: August 12, 2013Publication date: December 12, 2013Applicant: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Hiroaki Ohkubo, Mitsuji Okada, Shigeharu Nakata, Shuuichi Kagawa
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Patent number: 8534563Abstract: An exemplary aspect of the present invention is a memory card that includes: a memory that stores data; a driver that modulates the data stored in the memory; a transmitter that transmits the data modulated by the driver to a receiver provided in an external main unit; and an IC chip having the driver and the transmitter formed therein.Type: GrantFiled: October 14, 2010Date of Patent: September 17, 2013Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Hiroaki Ohkubo, Mitsuji Okada, Shigeharu Nakata, Shuuichi Kagawa
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Patent number: 8461907Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.Type: GrantFiled: December 6, 2012Date of Patent: June 11, 2013Assignee: Renesas Electronics CorporationInventors: Hiroaki Ohkubo, Yasutaka Nakashiba
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Patent number: 8416330Abstract: The solid state image pick-up device comprises a chip wherein an object to be photographed is put directly on the back surface of the chip, a light incident on the object enters the inner portion of the chip, signal electric charges generated in the inner portion of the chip by the light, the signal electric charges are collected in a photo detective region and the photo detective region has a barrier diffusion layer adjacent thereto so as to collect the signal electric charges effectively. The above-mentioned structure of the solid state image pick-up device can provide superior features that the chip of the solid state image pick-up device is protected from the deterioration of elements included in the chip and the destruction of the elements by Electro Static Discharge, resulting in the reliability improvement of the chip.Type: GrantFiled: July 16, 2012Date of Patent: April 9, 2013Assignee: Renesas Electronics CorporationInventors: Hiroaki Ohkubo, Yasutaka Nakashiba
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Patent number: 8357990Abstract: A width of a region where each of the N wells is in contact with the buried P well is not more than 2 ?m. A ground voltage and a power supply voltage are applied to the P well and the N well, respectively. A decoupling capacitor is formed between the N well and the buried P well.Type: GrantFiled: July 1, 2009Date of Patent: January 22, 2013Assignee: Renesas Electronics CorporationInventors: Masayuki Furumiya, Hiroaki Ohkubo, Yasutaka Nakashiba
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Patent number: 8339182Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.Type: GrantFiled: June 21, 2012Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Hiroaki Ohkubo, Yasutaka Nakashiba
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Patent number: 8330254Abstract: A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling.Type: GrantFiled: December 28, 2009Date of Patent: December 11, 2012Assignees: Renesas Electronics Corporation, NEC CorporationInventors: Masayuki Furumiya, Hiroaki Ohkubo, Fuyuki Okamoto, Masayuki Mizuno, Koichi Nose, Yoshihiro Nakagawa, Yoshio Kameda
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Publication number: 20120281125Abstract: The solid state image pick-up device comprises a chip wherein an object to be photographed is put directly on the back surface of the chip, a light incident on the object enters the inner portion of the chip, signal electric charges generated in the inner portion of the chip by the light, the signal electric charges are collected in a photo detective region and the photo detective region has a barrier diffusion layer adjacent thereto so as to collect the signal electric charges effectively. The above-mentioned structure of the solid state image pick-up device can provide superior features that the chip of the solid state image pick-up device is protected from the deterioration of elements included in the chip and the destruction of the elements by Electro Static Discharge, resulting in the reliability improvement of the chip.Type: ApplicationFiled: July 16, 2012Publication date: November 8, 2012Inventors: Hiroaki Ohkubo, Yasutaka Nakashiba
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Publication number: 20120262223Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.Type: ApplicationFiled: June 21, 2012Publication date: October 18, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroaki OHKUBO, Yasutaka NAKASHIBA
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Patent number: 8233063Abstract: The solid state image pick-up device comprises a chip wherein an object to be photographed is put directly on the back surface of the chip, a light incident on the object enters the inner portion of the chip, signal electric charges generated in the inner portion of the chip by the light, the signal electric charges are collected in a photo detective region and the photo detective region has a barrier diffusion layer adjacent thereto so as to collect the signal electric charges effectively. The above-mentioned structure of the solid state image pick-up device can provide superior features that the chip of the solid state image pick-up device is protected from the deterioration of elements included in the chip and the destruction of the elements by Electro Static Discharge, resulting in the reliability improvement of the chip.Type: GrantFiled: November 7, 2005Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Hiroaki Ohkubo, Yasutaka Nakashiba
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Patent number: 8217709Abstract: A semiconductor device includes a signal output unit, and a decision unit. The signal output unit includes m (?2) pieces of fuses, a NAND gate, resistance elements, and an output terminal. The decision unit decides whether n or more pieces (m?n?2) of fuses are disconnected out of the m pieces of fuses included in the signal output unit, and outputs the result of a decision. When m=n=2, the decision unit is constituted of a NOR gate having two input terminals connected to a respective end of the fuses. Thus, a H-level potential signal is output at an output terminal of the NOR gate when the decision result is affirmative. On the other hand, when the decision result is negative, a L-level potential signal is output at the output terminal.Type: GrantFiled: August 28, 2006Date of Patent: July 10, 2012Assignee: Renesas Electronics CorporationInventors: Hiroaki Ohkubo, Yasutaka Nakashiba
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Publication number: 20120133810Abstract: A solid state imaging device has a semiconductor substrate, a light receiving region provided on a surface layer on a first surface side of the semiconductor substrate, the light receiving region having a silicided surface, second impurity diffusion layer provided adjacent to the light receiving region on the surface layer on the first surface side of the semiconductor substrate, a gate insulating film provided adjacent to the second impurity diffusion layer on the first surface of the semiconductor substrate, a gate electrode provided on the gate insulating film, and a third impurity diffusion layer provided on an opposite side to the second impurity diffusion layer, with the gate insulating film and the gate electrode sandwiched.Type: ApplicationFiled: February 2, 2012Publication date: May 31, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroaki OHKUBO, Yasutaka Nakashiba
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Patent number: 8188566Abstract: The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.Type: GrantFiled: March 30, 2011Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventors: Masayuki Furumiya, Hiroaki Ohkubo, Yasutaka Nakashiba
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Patent number: 8130297Abstract: A solid state imaging device having a light receiving region on a first surface side of a semiconductor substrate, incident light from an object to be imaged being illuminated on a second surface side of the semiconductor substrate, the solid state imaging device including an impurity diffusion layer formed on the first surface side of the semiconductor substrate, a surface of the impurity diffusion layer being silicided, and a gate electrode formed on the first surface side of the semiconductor substrate. The impurity diffusion layer includes the light receiving region disposed on the first surface side of the semiconductor substrate, a surface of the light receiving region being silicided, and the impurity diffusion layer includes at least a surface adjacent to the gate electrode.Type: GrantFiled: August 16, 2010Date of Patent: March 6, 2012Assignee: Renesas Electronics CorporationInventors: Hiroaki Ohkubo, Yasutaka Nakashiba
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Publication number: 20110175196Abstract: The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Inventors: Masayuki FURUMIYA, Hiroaki Ohkubo, Yasutaka Nakashiba
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Patent number: 7973383Abstract: The bottom side of an N type silicon substrate is connected to a power supply terminal, a second P type epitaxial layer is formed on all sides of the N type silicon substrate, and a device forming portion is provided on the second P type epitaxial layer. A first P type epitaxial layer and an interlayer insulating film are provided on the device forming portion and an N well and a P well are formed on the top surface of the first P type epitaxial layer. The second P type epitaxial layer is connected to a ground terminal via the first P type epitaxial layer, the P well, a p+ diffusion region, a via and a wire. Accordingly, a pn junction is formed at the interface between the second P type epitaxial layer and the N type silicon substrate.Type: GrantFiled: September 24, 2007Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Masayuki Furumiya, Hiroaki Ohkubo, Yasutaka Nakashiba