Patents by Inventor Hiroaki Yamashita
Hiroaki Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9496334Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, an insulating layer, and a first electrode. The first semiconductor layer includes first semiconductor regions. The second semiconductor regions are provided respectively between the first semiconductor regions. The insulating layer is provided between the gate electrode and the third semiconductor region. The first electrode includes a first portion and a second portion. The first portion is connected to the first semiconductor region. The second portion is provided on the fourth semiconductor region side of the first portion. The first electrode is provided on the first semiconductor region and on the second semiconductor region.Type: GrantFiled: August 14, 2015Date of Patent: November 15, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroaki Yamashita, Syotaro Ono, Hideyuki Ura, Masahiro Shimura
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Publication number: 20160276427Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, an insulating layer, and a first electrode. The first semiconductor layer includes first semiconductor regions. The second semiconductor regions are provided respectively between the first semiconductor regions. The insulating layer is provided between the gate electrode and the third semiconductor region. The first electrode includes a first portion and a second portion. The first portion is connected to the first semiconductor region. The second portion is provided on the fourth semiconductor region side of the first portion. The first electrode is provided on the first semiconductor region and on the second semiconductor region.Type: ApplicationFiled: August 14, 2015Publication date: September 22, 2016Inventors: Hiroaki Yamashita, Syotaro Ono, Hideyuki Ura, Masahiro Shimura
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Patent number: 9437728Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.Type: GrantFiled: October 13, 2015Date of Patent: September 6, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
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Publication number: 20160254379Abstract: According to one embodiment, a semiconductor device includes a plurality of first semiconductor regions of a first conductivity type, a plurality of second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the second conductivity type, a fifth semiconductor region of the first conductivity type, and a gate electrode. An impurity concentration of the second conductivity type of the third semiconductor region is higher than an impurity concentration of the second conductivity type of the second semiconductor regions. The fourth semiconductor region is provided on the first semiconductor regions. The gate electrode provided on the fourth semiconductor region with a gate insulation layer interposed. The gate electrode extends in a third direction. The third direction intersects the first direction. The third direction is parallel to a plane including the first direction and the second direction.Type: ApplicationFiled: August 20, 2015Publication date: September 1, 2016Inventors: Hiroaki Yamashita, Syotaro Ono, Hideyuki Ura, Masahiro Shimura
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Patent number: 9349721Abstract: A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.Type: GrantFiled: April 7, 2014Date of Patent: May 24, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Hiroaki Yamashita
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Patent number: 9312331Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided in the first semiconductor region, an element region, and a termination region. The element region includes a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, and a gate electrode disposed on a gate insulating layer that extends adjacent the third semiconductor region and the fourth semiconductor region. The termination region surrounds the element region and includes a first electrode, which includes first portions extending in a first direction and second portions extending in a second direction. A plurality of first electrodes are provided on the first semiconductor region and the second semiconductor region. An interval between adjacent first portions in the second direction is less than an interval between adjacent second portions in the first direction.Type: GrantFiled: March 3, 2015Date of Patent: April 12, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hiroaki Yamashita, Syotaro Ono, Hideyuki Ura, Masaru Izumisawa
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Publication number: 20160079351Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type provided in the first semiconductor region, an element region, and a termination region. The element region includes a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, and a gate electrode disposed on a gate insulating layer that extends adjacent the third semiconductor region and the fourth semiconductor region. The termination region surrounds the element region and includes a first electrode, which includes first portions extending in a first direction and second portions extending in a second direction. A plurality of first electrodes are provided on the first semiconductor region and the second semiconductor region. An interval between adjacent first portions in the second direction is less than an interval between adjacent second portions in the first direction.Type: ApplicationFiled: March 3, 2015Publication date: March 17, 2016Inventors: Hiroaki YAMASHITA, Syotaro ONO, Hideyuki URA, Masaru IZUMISAWA
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Publication number: 20160079350Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, an element region, a terminal region, and a second electrode. The element region includes a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, and a first electrode. The terminal region includes a fifth semiconductor region of the second conductivity type, and a sixth semiconductor region of the second conductivity type. The terminal region surrounds the element region. The fifth semiconductor region is provided within the first semiconductor region. A plurality of the fifth semiconductor regions are provided along a second direction. The sixth semiconductor region is provided between the first semiconductor region and the fifth semiconductor region. A dopant of the sixth semiconductor region is higher than a dopant concentration of the fifth semiconductor region.Type: ApplicationFiled: February 17, 2015Publication date: March 17, 2016Inventors: Hiroshi OHTA, Masaru IZUMISAWA, Syotaro ONO, Hiroaki YAMASHITA, Takashi OKUHATA
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Publication number: 20160043213Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.Type: ApplicationFiled: October 13, 2015Publication date: February 11, 2016Inventors: Wataru SAITO, Syotaro ONO, Toshiyuki NAKA, Shunji TANIUCHI, Miho WATANABE, Hiroaki YAMASHITA
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Publication number: 20160043199Abstract: According to a method of manufacturing a semiconductor device of embodiments, a first trench is formed in a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type is formed in the first trench by using an epitaxial growth method, a second trench is formed in the second semiconductor layer, the second trench having a smaller depth than the first trench, a third semiconductor layer of the second conductivity type is formed in the second trench by using the epitaxial growth method, a gate insulating film is formed on the third semiconductor layer, a gate electrode is formed on the gate insulating film, and a first semiconductor region of the first conductivity type is formed in the third semiconductor layer.Type: ApplicationFiled: February 19, 2015Publication date: February 11, 2016Inventors: Yasuto Sumi, Hiroaki Yamashita
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Publication number: 20160035879Abstract: In general, according to one embodiment, a semiconductor device includes, a first semiconductor region, a plurality of second semiconductor regions, a plurality of third semiconductor regions, a fourth semiconductor region, a fifth semiconductor region, and a gate electrode. The third semiconductor region includes a first portion and a second portion. The first portion is provided between the second semiconductor regions adjacent to each other. An amount of impurity of the second conductivity type in the first portion is greater than an amount of impurity of the first conductivity type in the second semiconductor region contiguous to the first portion. The second portion is arranged with a part of the first semiconductor region. An amount of impurity of the second conductivity type in the second portion is smaller than an amount of impurity of the first conductivity type in the part of the first semiconductor region.Type: ApplicationFiled: March 9, 2015Publication date: February 4, 2016Inventors: Syotaro Ono, Hideyuki Ura, Masahiro Shimura, Hiroaki Yamashita
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Publication number: 20150380545Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type having an effective impurity concentration that is less than an effective impurity concentration of the first semiconductor layer arranged on the first semiconductor layer, a third semiconductor layer of a second conductivity type arranged on the second semiconductor layer, and a gate electrode formed in the first second semiconductor layer and the third semiconductor layer, wherein at least two regions are formed in the power semiconductor device, and a threshold voltage of the first region is different from a threshold voltage of the second region.Type: ApplicationFiled: September 10, 2015Publication date: December 31, 2015Inventors: Hiroaki YAMASHITA, Masaru IZUMISAWA, Syotaro ONO, Hiroshi OHTA
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Publication number: 20150341568Abstract: A video display apparatus includes video output units to output signals representing first videos captured or received, respectively, and when a predetermined signal is input from an outside, only for a predetermined period, to output signals representing second videos having fixed images, instead of the signals representing the first videos, respectively; a display to display a video based on the signal output by one of the video output units; and a control apparatus to output the predetermined signal to the video output units, and after having output the predetermined signal, to execute switching a signal representing a video output to the display among the signals representing the videos output by the video output units, while the video output units having the signals representing the videos output to the display before and after the switching, respectively, output the signals representing the second videos, respectively.Type: ApplicationFiled: March 30, 2015Publication date: November 26, 2015Inventors: Hiroaki YAMASHITA, Goro ASAI, Makoto NISHIDA, Yohei SATOMI, Masaaki AMANO, Yuka SHIDOCHI
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Patent number: 9196721Abstract: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.Type: GrantFiled: July 11, 2014Date of Patent: November 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita
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Patent number: 9142627Abstract: A semiconductor device includes a first layer of a first conductivity type between a first and a second electrode. A second layer of the first conductivity type is between the first layer and the second electrode. A pair of third layers of a second conductivity type has a first portion in the first layer and a second portion contacting the second layer. A fourth layer is between the second layer and the second electrode and between the third layers and the second electrode. A fifth layer is between the fourth layer and the second electrode. A third electrode is adjacent to the second layer via a first insulating film. A fourth electrode is between the second electrode and the third electrode and adjacent to the fourth semiconductor layer via a second insulating film. The second insulating film is thinner than the first insulating film.Type: GrantFiled: August 29, 2014Date of Patent: September 22, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Syotaro Ono, Masaru Izumisawa, Hideyuki Ura, Hiroaki Yamashita
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Publication number: 20150264346Abstract: A video encoding device includes: a processor configured to execute a process including: when successively encoding a plurality of blocks obtained by dividing a frame image in a predetermined period, selecting an encoding mode by which each block is encoded, in accordance with a progress status of encoding of the blocks; and successively encoding each block of the frame image in the selected encoding mode.Type: ApplicationFiled: February 27, 2015Publication date: September 17, 2015Inventors: Hiroaki Yamashita, YASUO MISUDA
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Patent number: 9136351Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.Type: GrantFiled: August 21, 2014Date of Patent: September 15, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Hiroaki Yamashita
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Patent number: 9093474Abstract: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.Type: GrantFiled: August 31, 2012Date of Patent: July 28, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Toshiyuki Naka, Shunji Taniuchi, Hiroaki Yamashita
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Publication number: 20150200248Abstract: A semiconductor device includes a first layer of a first conductivity type between a first and a second electrode. A second layer of the first conductivity type is between the first layer and the second electrode. A pair of third layers of a second conductivity type has a first portion in the first layer and a second portion contacting the second layer. A fourth layer is between the second layer and the second electrode and between the third layers and the second electrode. A fifth layer is between the fourth layer and the second electrode. A third electrode is adjacent to the second layer via a first insulating film. A fourth electrode is between the second electrode and the third electrode and adjacent to the fourth semiconductor layer via a second insulating film. The second insulating film is thinner than the first insulating film.Type: ApplicationFiled: August 29, 2014Publication date: July 16, 2015Inventors: Syotaro ONO, Masaru IZUMISAWA, Hideyuki URA, Hiroaki YAMASHITA
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Patent number: 9059284Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type. A second semiconductor layer of a second conductivity type is on the first semiconductor layer. A third semiconductor layer is on the second semiconductor layer. A fourth semiconductor layer is selectively in the first semiconductor layer. A first trench and second trench penetrate from a surface of the third layer through the second layer to reach the first layer. An embedded electrode is in the first trench. A control electrode is above the embedded electrode via an insulating film. A lower end of the second trench is connected to the fourth semiconductor layer. A first main electrode is electrically connected to the first layer. A second main electrode is provided in the second trench. A Schottky junction is formed by the first layer and the second main electrode at a sidewall of the second trench.Type: GrantFiled: December 16, 2013Date of Patent: June 16, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Wataru Saito, Syotaro Ono, Shunji Taniuchi, Miho Watanabe, Hiroaki Yamashita