Patents by Inventor Hiroharu Shimizu

Hiroharu Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9397083
    Abstract: There is provided a technique capable of reducing a layout area of a standard cell configuring a digital circuit even under a circumstance that a new layout rule introduced in accordance with microfabrication of a MISFET is provided. For example, a protruding wiring PL1A protrudes from a power supply wiring L1A at each corner of both ends of a standard cell CL toward an inside of the standard cell CL (in a Y direction), and a bent portion BD1A which is bent from the protruding wiring PL1A in an X direction is formed. And, this bent portion BD1A and a p-type semiconductor region PDR are connected to each other via a plug PLG.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: July 19, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroharu Shimizu
  • Patent number: 8618579
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: December 31, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroharu Shimizu, Masakazu Nishibori, Toshihiko Ochiai
  • Patent number: 8566763
    Abstract: A computer device which performs logic synthesis using hardware description and a component in a cell library and generates a net list of a logic circuit including a series path of a clock synchronous sequential circuit and a combinational circuit performs optimization processing for decreasing the number of gate stages in a critical path between sequential circuits in the data path by using a third sequential circuit having a negative-logic input terminal and a negative-logic non-inverted output terminal and a fourth sequential circuit having a negative-logic input terminal and a negative-logic inverted output terminal in addition to a first sequential circuit having a positive-logic input terminal and a positive-logic non-inverted output terminal and a second sequential circuit having a positive-logic input terminal and a positive-logic inverted output terminal.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: October 22, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroharu Shimizu, Yasuhiro Yadoguchi
  • Patent number: 8410526
    Abstract: A semiconductor integrated circuit device with reduced cell size including a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or (an integer+0.25×a wiring pitch of the second-layer wiring lines.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: April 2, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroharu Shimizu
  • Patent number: 8399929
    Abstract: To provide a technique that can maintain uniformity of semiconductor elements and wirings microfabricated, while maintaining the mounting efficiency of circuit cells onto a chip. Respective gate electrodes of an n-channel type MISFET and another n-channel type MISFET forming a NAND circuit cell are coupled to the same node, and simultaneously perform respective on-off operations according to the same input signal. These n-channel type MISFETs are arranged adjacent to each other, and electrically coupled in series. Respective gate electrodes of a p-channel type MISFET and another p-channel type MISFET forming the NAND circuit cell are coupled to the same node, and simultaneously perform respective on-off operations according to the same input signal. These p-channel type MISFETs are arranged adjacent to each other, and electrically coupled in series.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: March 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroharu Shimizu
  • Patent number: 8354697
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: January 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroharu Shimizu, Masakazu Nishibori, Toshihiko Ochiai
  • Publication number: 20120299065
    Abstract: There is provided a technique capable of reducing a layout area of a standard cell configuring a digital circuit even under a circumstance that a new layout rule introduced in accordance with microfabrication of a MISFET is provided. For example, a protruding wiring PL1A protrudes from a power supply wiring L1A at each corner of both ends of a standard cell CL toward an inside of the standard cell CL (in a Y direction), and a bent portion BD1A which is bent from the protruding wiring PL1A in an X direction is formed. And, this bent portion BD1A and a p-type semiconductor region PDR are connected to each other via a plug PLG.
    Type: Application
    Filed: February 3, 2010
    Publication date: November 29, 2012
    Inventor: Hiroharu Shimizu
  • Publication number: 20120274354
    Abstract: A computer device which performs logic synthesis using hardware description and a component in a cell library and generates a net list of a logic circuit including a series path of a clock synchronous sequential circuit and a combinational circuit performs optimization processing for decreasing the number of gate stages in a critical path between sequential circuits in the data path by using a third sequential circuit having a negative-logic input terminal and a negative-logic non-inverted output terminal and a fourth sequential circuit having a negative-logic input terminal and a negative-logic inverted output terminal in addition to a first sequential circuit having a positive-logic input terminal and a positive-logic non-inverted output terminal and a second sequential circuit having a positive-logic input terminal and a positive-logic inverted output terminal.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroharu SHIMIZU, Yasuhiro YADOGUCHI
  • Publication number: 20120211840
    Abstract: A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].
    Type: Application
    Filed: May 1, 2012
    Publication date: August 23, 2012
    Inventor: Hiroharu Shimizu
  • Patent number: 8183600
    Abstract: A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: May 22, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroharu Shimizu
  • Publication number: 20120007189
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Inventors: HIROHARU SHIMIZU, Masakazu Nishibori, Toshihiko Ochiai
  • Patent number: 8043900
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Grant
    Filed: August 23, 2009
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroharu Shimizu, Masakazu Nishibori, Toshihiko Ochiai
  • Publication number: 20100148219
    Abstract: A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].
    Type: Application
    Filed: December 7, 2009
    Publication date: June 17, 2010
    Inventor: Hiroharu SHIMIZU
  • Publication number: 20100059826
    Abstract: To provide a technique that can maintain uniformity of semiconductor elements and wirings microfabricated, while maintaining the mounting efficiency of circuit cells onto a chip. Respective gate electrodes of an n-channel type MISFET and another n-channel type MISFET forming a NAND circuit cell are coupled to the same node, and simultaneously perform respective on-off operations according to the same input signal. These n-channel type MISFETs are arranged adjacent to each other, and electrically coupled in series. Respective gate electrodes of a p-channel type MISFET and another p-channel type MISFET forming the NAND circuit cell are coupled to the same node, and simultaneously perform respective on-off operations according to the same input signal. These p-channel type MISFETs are arranged adjacent to each other, and electrically coupled in series.
    Type: Application
    Filed: August 12, 2009
    Publication date: March 11, 2010
    Inventor: Hiroharu SHIMIZU
  • Publication number: 20100059794
    Abstract: To provide a circuit layout design method that can prevent degradation of the circuit reliability even in highly miniaturized circuit cells. In order to prevent noise from a power supply potential or a reference potential with a large potential difference from affecting a gate electrode and causing a malfunction, a first plug connected to the gate electrode and a second plug to which the power supply potential or the reference potential is supplied are required to be spaced from each other by a distance sufficient for the noise from the power supply potential or the reference potential not to affect the first plug. To this end, among the second plugs placed at equal intervals under the wiring, only the second plug placed at a layout position that is not sufficiently spaced from the first plug is deleted at the time of planar layout design.
    Type: Application
    Filed: August 23, 2009
    Publication date: March 11, 2010
    Inventors: Hiroharu SHIMIZU, Masakazu Nishibori, Toshihiko Ochiai