Patents by Inventor Hirohisa Kawasaki

Hirohisa Kawasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070170474
    Abstract: A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate; a non-planar type transistor region having at least one of a fin type transistor region including a fin type transistor in which a current is induced to flow through side faces of a fin formed approximately vertically to a surface of the semiconductor substrate in a direction approximately parallel to the surface of the semiconductor substrate, and a tri-gate type transistor region including a tri-gate type transistor in which a channel is formed in three surfaces having side faces and an upper surface of a fin formed approximately vertically to the surface of the semiconductor substrate, and thus a current is induced to flow through the three surfaces in a direction approximately parallel to the surface of the semiconductor substrate; and a filling material for isolation in the non-planar type transistor region within the semiconductor substrate and which has a plurality of regions having differen
    Type: Application
    Filed: January 23, 2007
    Publication date: July 26, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hirohisa KAWASAKI
  • Publication number: 20070164364
    Abstract: A semiconductor device includes a first semiconductor layer, an n-type/p-type second semiconductor layer, p-type/n-type third semiconductor layers and a first gate electrode. The second semiconductor layer is formed on the first semiconductor layer and has an oxidation rate which is lower than that of the first semiconductor layer. The third semiconductor layers are formed in the second semiconductor layer and have a depth reaching an inner part of the first semiconductor layer. In case that the second and third semiconductor layers are n-type and p-type, respectively, a lattice constant of the second semiconductor layer is less than that of the third semiconductor layer. In case that the second and third semiconductor layers are p-type and n-type, respectively, the lattice constant of the second semiconductor layer is greater than that of the third semiconductor layer. A first gate electrode is formed on the second semiconductor layer.
    Type: Application
    Filed: January 4, 2007
    Publication date: July 19, 2007
    Inventor: Hirohisa Kawasaki
  • Publication number: 20070090468
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
    Type: Application
    Filed: December 12, 2006
    Publication date: April 26, 2007
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru
  • Patent number: 7164175
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: January 16, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru
  • Publication number: 20050282354
    Abstract: A semiconductor device manufacturing method is disclosed. The method is to form a second semiconductor layer which has less susceptibility to adopting insulative characteristics than a first semiconductor layer on the first semiconductor layer. Then, grooves which expose portions of the second and first semiconductor layers are formed to extend from the upper surface of the second semiconductor layer into the first semiconductor layer. Next, portions of the first and second semiconductor layers which are exposed to the grooves are changed into an insulator form to fill the grooves with the insulator-form portions of the first semiconductor layer.
    Type: Application
    Filed: March 25, 2005
    Publication date: December 22, 2005
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru, Kunihiro Kasai, Yasunori Okayama
  • Publication number: 20050133819
    Abstract: A semiconductor device includes a substrate-strained Si formed of a first semiconductor layer which has a first lattice constant and formed on a semiconductor substrate, and a second semiconductor layer which has a second lattice constant and epitaxially grows such that a lattice of the second semiconductor layer matches that of the first semiconductor layer. The semiconductor device further includes a first conductive type metal oxide semiconductor (MOS) transistor which is formed in a first region on the substrate-strained Si and has the second semiconductor layer modified so as to have a first thickness, and a second conductive type MOS transistor which is formed in a second region on the substrate-strained Si and has the second semiconductor layer modified-so as to have a second thickness thinner than the first thickness.
    Type: Application
    Filed: October 25, 2004
    Publication date: June 23, 2005
    Inventor: Hirohisa Kawasaki
  • Publication number: 20050082628
    Abstract: A semiconductor device which is here disclosed includes a first wiring layer having a first lower end and a first upper end protruded more than the first lower end, and a second wiring layer having a second lower end and a second upper end protruded more than the second lower end, the second upper end facing the first upper end with the interposition of a first gap, and the second lower end facing the first lower end with the interposition of a second gap larger than the first gap.
    Type: Application
    Filed: December 19, 2003
    Publication date: April 21, 2005
    Inventors: Hirohisa Kawasaki, Kazuaki Isobe
  • Publication number: 20050026377
    Abstract: A semiconductor device includes a semiconductor substrate, an insulating film projected on a surface of the semiconductor substrate, a semiconductor film provided on a side surface of the insulating film, and MIS transistor formed in the semiconductor film, the MIS transistor having source, gate and drain region. The semiconductor device further includes a gate electrode provided on the gate region of the MIS transistor, the length of the gate electrode being larger than the thickness of the semiconductor film.
    Type: Application
    Filed: April 28, 2004
    Publication date: February 3, 2005
    Inventors: Hirohisa Kawasaki, Kazunari Ishimaru