Patents by Inventor Hirokazu Honda

Hirokazu Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11366390
    Abstract: An extreme ultraviolet light generation system may include a laser system emitting first prepulse laser light, second prepulse laser light, and main pulse laser light in this order; a chamber including at least one window for introducing, into the chamber, the first prepulse laser light, the second prepulse laser light, and the main pulse laser light; a target supply unit supplying a target to a predetermined region in the chamber; and a processor controlling the laser system to irradiate the target with the first prepulse laser light, irradiate the target, having been irradiated with the first prepulse laser light, with the second prepulse laser light having a pulse time width longer than a pulse time width of the main pulse laser light, and irradiate the target, having been irradiated with the second prepulse laser light, with the main pulse laser light temporally separated from the second prepulse laser light.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: June 21, 2022
    Assignee: Gigaphoton Inc.
    Inventors: Takanari Kobayashi, Hirokazu Hosoda, Yoshiyuki Honda
  • Patent number: 10098179
    Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: October 9, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Hirokazu Honda, Masaki Watanabe, Junichi Arita, Norio Okada, Jun Ueno, Masashi Nishimoto, Michitaka Kimura, Tomohiro Nishiyama
  • Patent number: 9635762
    Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: April 25, 2017
    Assignee: J-DEVICES CORPORATION
    Inventors: Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Hiroshi Demachi, Takeshi Miyakoshi, Tomoshige Chikai, Kiminori Ishido, Hiroaki Matsubara, Takashi Nakamura, Hirokazu Honda, Yoshikazu Kumagaya, Shotaro Sakumoto, Toshihiro Iwasaki, Michiaki Tamakawa
  • Patent number: 9368474
    Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickn
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: June 14, 2016
    Assignee: J-DEVICES CORPORATION
    Inventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
  • Patent number: 9362200
    Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: June 7, 2016
    Assignee: J-DEVICES CORPORATION
    Inventors: Hirokazu Honda, Shinji Watanabe, Toshihiro Iwasaki, Kiminori Ishido, Koichiro Niwa, Takeshi Miyakoshi, Sumikazu Hosoyamada, Yoshikazu Kumagaya, Tomoshige Chikai, Shingo Nakamura, Shotaro Sakumoto, Hiroaki Matsubara
  • Patent number: 9362262
    Abstract: This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: June 7, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Manabu Okamoto, Hirokazu Honda
  • Publication number: 20160079204
    Abstract: A manufacturing method for a semiconductor device of the present invention includes: preparing a semiconductor wafer including an electrode formed therein; electrically connecting a first semiconductor element formed in a semiconductor chip and the electrode formed in the semiconductor wafer; filling a gap between the semiconductor wafer and the semiconductor chip with a first insulating resin layer; forming a second insulating resin layer on the semiconductor wafer; grinding the second insulating resin layer and the semiconductor chip until a thickness of the semiconductor chip reaches a predetermined thickness; forming a first insulating layer on the second insulating resin layer and the semiconductor chip; forming a line on the first insulating layer connected with a conductive material filled an opening in the first insulating layer and the second insulating resin layer to expose the electrode; and grinding the semiconductor wafer until a thickness of the semiconductor wafer reaches a predetermined thickn
    Type: Application
    Filed: September 10, 2015
    Publication date: March 17, 2016
    Inventors: Hiroaki Matsubara, Tomoshige Chikai, Kiminori Ishido, Takashi Nakamura, Hirokazu Honda, Hiroshi Demachi, Yoshikazu Kumagaya, Shotaro Sakumoto, Shinji Watanabe, Sumikazu Hosoyamada, Shingo Nakamura, Takeshi Miyakoshi, Toshihiro Iwasaki, Michiaki Tamakawa
  • Publication number: 20160027715
    Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.
    Type: Application
    Filed: July 20, 2015
    Publication date: January 28, 2016
    Inventors: Shinji WATANABE, Sumikazu HOSOYAMADA, Shingo NAKAMURA, Hiroshi DEMACHI, Takeshi MIYAKOSHI, Tomoshige CHIKAI, Kiminori ISHIDO, Hiroaki MATSUBARA, Takashi NAKAMURA, Hirokazu HONDA, Yoshikazu KUMAGAYA, Shotaro SAKUMOTO, Toshihiro IWASAKI, Michiaki TAMAKAWA
  • Publication number: 20150371934
    Abstract: A semiconductor package includes a support substrate arranged with a first aperture reaching a semiconductor device on a rear side, the semiconductor device is bonded via an adhesive to a surface of the support substrate, an insulating layer covering the semiconductor device, and wiring for connecting the semiconductor device and an external terminal through the insulating layer. The adhesive may form a part of the first aperture. In addition, a heat dissipation part may be arranged in the first aperture and a metal material may be filled in the first aperture.
    Type: Application
    Filed: June 19, 2015
    Publication date: December 24, 2015
    Inventors: Hirokazu HONDA, Shinji WATANABE, Toshihiro IWASAKI, Kiminori ISHIDO, Koichiro NIWA, Takeshi MIYAKOSHI, Sumikazu HOSOYAMADA, Yoshikazu KUMAGAYA, Tomoshige CHIKAI, Shingo NAKAMURA, Shotaro SAKUMOTO, Hiroaki MATSUBARA
  • Publication number: 20150333048
    Abstract: This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction.
    Type: Application
    Filed: July 23, 2015
    Publication date: November 19, 2015
    Inventors: Shintaro Yamamichi, Manabu Okamoto, Hirokazu Honda
  • Patent number: 9117814
    Abstract: This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction.
    Type: Grant
    Filed: May 22, 2014
    Date of Patent: August 25, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Manabu Okamoto, Hirokazu Honda
  • Publication number: 20140361410
    Abstract: This invention prevents a substrate of a semiconductor chip that has through-silicon vias collectively arranged in a specific area thereof from becoming cracked. When a direction in parallel with a long side of a first semiconductor chip is defined as a row direction and a direction perpendicular to the long side of the first semiconductor chip is defined as a column direction, each one of the first through-silicon vias is arranged on any one of grid points arranged in m rows and n columns (m>n). In addition, as viewed in a cross section taken along a short side of the first semiconductor chip, the center of a through-silicon via area, which is defined by coupling the outermost grid points arranged in m rows and n columns, is off center of the short side of the first semiconductor chip in a first direction.
    Type: Application
    Filed: May 22, 2014
    Publication date: December 11, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Shintaro Yamamichi, Manabu Okamoto, Hirokazu Honda
  • Publication number: 20140329476
    Abstract: A compact electronic device as a constituent element of a wireless communication system using a sensor. A first feature of the device is that a first semiconductor chip is bare-chip-mounted over a front surface of a first wiring board in the form of a chip and a second semiconductor chip is bare-chip-mounted over a second wiring board in the form of a chip. A second feature is that a wireless communication unit and a data processing unit which configure a module are separately mounted. A third feature is that the first and second wiring boards are stacked in the board thickness direction to make up the module (electronic device).
    Type: Application
    Filed: April 22, 2014
    Publication date: November 6, 2014
    Applicants: RENESAS ELECTRONICS CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Shintaro YAMAMICHI, Hirokazu HONDA, Masaki WATANABE, Junichi ARITA, Norio OKADA, Jun UENO, Masashi NISHIMOTO, Michitaka KIMURA, Tomohiro NISHIYAMA
  • Patent number: 8389414
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: March 5, 2013
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Katsumi Kikuchi, Shintaro Yamamichi, Hideya Murai, Takuo Funaya, Kentaro Mori, Takehiko Maeda, Hirokazu Honda, Kenta Ogawa, Jun Tsukano
  • Patent number: 8324718
    Abstract: A semiconductor device includes: a semiconductor chip mounted on a mounting substrate; a first resin filling a gap between the chip and the substrate; a frame-shaped stiffener surrounding the chip; a first adhesive for bonding the stiffener to the substrate; a lid for covering the stiffener and an area surrounded by the stiffener; and a second resin filling a space between the stiffener and the chip. A thermal expansion coefficient of the second resin is smaller than that of the first resin. The first resin includes an underfill part filling a gap between the chip and the substrate and a fillet part extended from the chip region.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hirokazu Honda
  • Patent number: 8304905
    Abstract: A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: November 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Matsui, Tsuyoshi Eda, Akira Matsumoto, Yoshitaka Kyougoku, Shinji Watanabe, Hirokazu Honda
  • Patent number: 8198140
    Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 12, 2012
    Assignees: NEC Corporation, Renesas Electronics Corporation
    Inventors: Hideya Murai, Tadanori Shimoto, Takuo Funaya, Katsumi Kikuchi, Shintaro Yamamichi, Kazuhiro Baba, Hirokazu Honda, Keiichiro Kata, Kouji Matsui, Shinichi Miyazaki
  • Publication number: 20120025371
    Abstract: A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.
    Type: Application
    Filed: July 27, 2011
    Publication date: February 2, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Satoshi MATSUI, Tsuyoshi EDA, Akira MATSUMOTO, Yoshitaka KYOUGOKU, Shinji WATANABE, Hirokazu HONDA
  • Patent number: 8008130
    Abstract: In accordance with the present invention, during formation of the interconnection board, the interconnection board remains securely fixed to a high rigidity plate being higher in rigidity than the interconnection board for suppressing the interconnection board from being bent.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: August 30, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hirokazu Honda
  • Publication number: 20110136298
    Abstract: A wiring board has an insulating layer, a plurality of wiring layers formed in such a way as to be insulated from each other by the insulating layer, and a plurality of vias formed in the insulating layer to connect the wiring layers. Of the wiring layers, a surface wiring layer formed in one surface of the insulating layer include a first metal film exposed from the one surface and a second metal film embedded in the insulating layer and stacked on the first metal film. Edges of the first metal film project from edges of the second metal film in the direction in which the second metal film spreads. By designing the shape of the wiring layers embedded in the insulating layer in this manner, it is possible to obtain a highly reliable wiring board that can be effectively prevented from side etching in the manufacturing process and can adapt to miniaturization and highly dense packaging of wires.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Applicants: NEC CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Katsumi KIKUCHI, Shintaro YAMAMICHI, Hideya MURAI, Takuo FUNAYA, Kentaro MORI, Takehiko MAEDA, Hirokazu HONDA, Kenta OGAWA, Jun TSUKANO