Patents by Inventor Hirokazu Nagashima
Hirokazu Nagashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11022512Abstract: A measurement system (20) includes pressure measurement apparatuses (220, 221, 222) capable of measuring pressure. The pressure measurement apparatuses (220, 221, 222) measure pressure at a measurement timing designated by a trigger signal.Type: GrantFiled: May 13, 2019Date of Patent: June 1, 2021Assignees: YOKOGAWA ELECTRIC CORPORATION, Yokogawa Test & Measurement CorporationInventors: Hirokazu Nagashima, Tadahiko Iinuma, Hironori Kurihara, Hideki Yamada
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Patent number: 10620074Abstract: A pressure gauge includes: a pressure sensor; a display unit configured to display a measurement value of the pressure sensor; and a measurement controller configured to set, as a measurement range of the pressure sensor, any of a plurality of measurement ranges defined by a lower limit value specific to the pressure sensor and respective upper limit values that are equal to or lower than an upper limit value specific to the pressure sensor and are different from each other, and to avoid that the display unit displays the measurement value when the measurement value exceeds a display upper limit value dependent on the upper limit value of the measurement range that is set.Type: GrantFiled: December 1, 2017Date of Patent: April 14, 2020Assignees: Yokogawa Electric Corporation, Yokogawa Test & Measurement CorporationInventors: Hirokazu Nagashima, Tadahiko Iinuma, Toshiaki Kawakami
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Publication number: 20190346325Abstract: A measurement system (20) includes pressure measurement apparatuses (220, 221, 222) capable of measuring pressure. The pressure measurement apparatuses (220, 221, 222) measure pressure at a measurement timing designated by a trigger signal.Type: ApplicationFiled: May 13, 2019Publication date: November 14, 2019Applicants: YOKOGAWA ELECTRIC CORPORATION, Yokogawa Test & Measurement CorporationInventors: Hirokazu NAGASHIMA, Tadahiko IINUMA, Hironori KURIHARA, Hideki YAMADA
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Publication number: 20180202885Abstract: A pressure gauge includes: a pressure sensor; a display unit configured to display a measurement value of the pressure sensor; and a measurement controller configured to set, as a measurement range of the pressure sensor, any of a plurality of measurement ranges defined by a lower limit value specific to the pressure sensor and respective upper limit values that are equal to or lower than an upper limit value specific to the pressure sensor and are different from each other, and to avoid that the display unit displays the measurement value when the measurement value exceeds a display upper limit value dependent on the upper limit value of the measurement range that is set.Type: ApplicationFiled: December 1, 2017Publication date: July 19, 2018Applicants: Yokogawa Electric Corporation, Yokogawa Test & Measurement CorporationInventors: Hirokazu NAGASHIMA, Tadahiko IINUMA, Toshiaki KAWAKAMI
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Patent number: 8423705Abstract: A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area.Type: GrantFiled: June 13, 2008Date of Patent: April 16, 2013Assignee: Spansion LLCInventors: Hirokazu Nagashima, Kazuki Yamauchi, Junya Kawamata, Tsutomu Nakai, Kenji Arai, Kenichi Takehana
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Publication number: 20120023539Abstract: According to one embodiment, an information processing apparatus includes: an input module which receives an address of a content stored in a storage apparatus connected via a network; a managing module which stores the received address of the content and an identifier of the storage apparatus in such a manner that the address of the content and the identifier are correlated with each other; a receiving module configured to receive the identifier and an address of the storage apparatus from the storage apparatus after the input module received the address of the content; and an updating module which updates the address of the content which is correlated with an identifier that coincides with the identifier received by the receiving module among identifiers managed by the managing module, based on the address of the storage apparatus received by the receiving module.Type: ApplicationFiled: April 26, 2011Publication date: January 26, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: HIROKAZU NAGASHIMA
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Patent number: 7831644Abstract: According to one embodiment, an electronic apparatus includes a wireless communication device, an information acquisition module, a file management information generation module, and an access control module. The information acquisition module acquires, by wireless communication with an external device, metadata corresponding to content data which the external device can provide. The file management information generation module generates, based on the acquired metadata, file management information based on which a host apparatus recognizes the content data as a file stored in a storage medium in the electronic apparatus. The access control module is configured to, upon receiving a read request for a file corresponding to the content data, which is transmitted from the host apparatus, execute external device access processing of acquiring the content data from the external device using the wireless communication device, and output the acquired content data to the host apparatus.Type: GrantFiled: April 9, 2009Date of Patent: November 9, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuaki Moritani, Yasuhiro Morioka, Hiroki Iwahara, Naomiki Kobayashi, Hirokazu Nagashima
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Patent number: 7787312Abstract: A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.Type: GrantFiled: May 30, 2008Date of Patent: August 31, 2010Assignee: Spansion LLCInventors: Junya Kawamata, Tsutomu Nakai, Hirokazu Nagashima, Kenichi Takehana, Kenji Arai, Kazuki Yamauchi, Kazuhide Kurosaki
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Patent number: 7761614Abstract: According to one embodiment, an electronic apparatus is detachably connected to a host apparatus. The electronic apparatus includes a file management information generation module. The file management information generation module generates file management information based on which a host apparatus recognizes each of content data items as a file stored in a storage medium, the file management information being indicative of a plurality of starting storage locations on the storage medium corresponding to starting data blocks of the content data items, and a plurality of shared storage locations on the storage medium, which are shared by the content data items and correspond to second and following data blocks of each of the content data items.Type: GrantFiled: April 24, 2009Date of Patent: July 20, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hirokazu Nagashima, Mitsuaki Moritani, Yasuhiro Morioka, Hiroki Iwahara, Naomiki Kobayashi
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Publication number: 20100081382Abstract: According to one embodiment, a wireless communication apparatus includes a plurality of communication modules configured to execute wireless communication with an external device, a field strength measurement module configured to measure a field strength from the external device, which is received by each of the plurality of communication modules, a recognition module configured to recognize a movement log of the external device on the basis of a change state of the field strength in each of the plurality of communication modules, which is measured by the field strength measurement module, and a processing module configured to execute a process corresponding to the movement log recognized by the recognition module.Type: ApplicationFiled: May 21, 2009Publication date: April 1, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hirokazu Nagashima
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Patent number: 7679968Abstract: Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.Type: GrantFiled: May 29, 2008Date of Patent: March 16, 2010Assignee: Spansion LLCInventors: Kazuki Yamauchi, Junya Kawamata, Tsutomu Nakai, Kenji Arai, Hirokazu Nagashima, Kenichi Takehana
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Publication number: 20090292830Abstract: According to one embodiment, an electronic apparatus is detachably connected to a host apparatus. The electronic apparatus includes a file management information generation module. The file management information generation module generates file management information based on which a host apparatus recognizes each of content data items as a file stored in a storage medium, the file management information being indicative of a plurality of starting storage locations on the storage medium corresponding to starting data blocks of the content data items, and a plurality of shared storage locations on the storage medium, which are shared by the content data items and correspond to second and following data blocks of each of the content data items.Type: ApplicationFiled: April 24, 2009Publication date: November 26, 2009Inventors: Hirokazu Nagashima, Mitsuaki Moritani, Yasuhiro Morioka, Hiroki Iwahara, Naomiki Kobayashi
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Publication number: 20090292707Abstract: According to one embodiment, an electronic apparatus includes a wireless communication device, an information acquisition module, a file management information generation module, and an access control module. The information acquisition module acquires, by wireless communication with an external device, metadata corresponding to content data which the external device can provide. The file management information generation module generates, based on the acquired metadata, file management information based on which a host apparatus recognizes the content data as a file stored in a storage medium in the electronic apparatus. The access control module is configured to, upon receiving a read request for a file corresponding to the content data, which is transmitted from the host apparatus, execute external device access processing of acquiring the content data from the external device using the wireless communication device, and output the acquired content data to the host apparatus.Type: ApplicationFiled: April 9, 2009Publication date: November 26, 2009Inventors: Mitsuaki Moritani, Yusuhiro Morioka, Hiroki Iwahara, Naomiki Kobayashi, Hirokazu Nagashima
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Publication number: 20090010076Abstract: A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.Type: ApplicationFiled: May 30, 2008Publication date: January 8, 2009Applicant: SPANSION LLCInventors: Junya Kawamata, Tsutomu Nakai, Hirokazu Nagashima, Kenichi Takehana, Kenji Arai, Kazuki Yamauchi, Kazuhide Kurosaki
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Publication number: 20080320208Abstract: A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area.Type: ApplicationFiled: June 13, 2008Publication date: December 25, 2008Applicant: SPANSION LLCInventors: Hirokazu Nagashima, Kazuki Yamauchi, Junya Kawamata, Tsutomu Nakai, Kenji Arai, Kenichi Takehana
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Publication number: 20080298136Abstract: Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.Type: ApplicationFiled: May 29, 2008Publication date: December 4, 2008Inventors: Kazuki Yamauchi, Junya Kawamata, Tsutomu Nakai, Kenji Arai, Hirokazu Nagashima, Kenichi Takehana
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Patent number: 6826081Abstract: In a block which is a target of detection of flag data, a page buffer 100 reads data of memory cells 42 of each memory cell by block unit, and latches the data. A detection circuit 28 performs detection of the flag data for each block based on output of the page buffers 100 of one block.Type: GrantFiled: August 12, 2003Date of Patent: November 30, 2004Assignee: Fujitsu LimitedInventors: Hirokazu Nagashima, Shoichi Kawamura
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Patent number: 6788588Abstract: An asynchronous semiconductor memory device includes an output circuit, which outputs data read from a memory unit, and a high impedance control circuit. The high impedance circuit is connected to the output circuit, stores a burst completion address, and compares a present address with the burst completion address. The high impedance control circuit causes a data output terminal of the output circuit to enter a high impedance state when the present address substantially coincides with the burst completion address. Due to the high impedance control circuit, an exclusive terminal for high impedance control is not necessary.Type: GrantFiled: January 16, 2003Date of Patent: September 7, 2004Assignee: Fujitsu LimitedInventors: Kenji Nagai, Hirokazu Nagashima
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Publication number: 20040042280Abstract: In a block which is a target of detection of flag data, a page buffer 100 reads data of memory cells 42 of each memory cell by block unit, and latches the data. A detection circuit 28 performs detection of the flag data for each block based on output of the page buffers 100 of one block.Type: ApplicationFiled: August 12, 2003Publication date: March 4, 2004Applicant: FUJITSU LIMITEDInventors: Hirokazu Nagashima, Shoichi Kawamura
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Publication number: 20030174543Abstract: An asynchronous semiconductor memory device includes an output circuit, which outputs data read from a memory unit, and a high impedance control circuit. The high impedance circuit is connected to the output circuit, stores a burst completion address, and compares a present address with the burst completion address. The high impedance control circuit causes a data output terminal of the output circuit to enter a high impedance state when the present address substantially coincides with the burst completion address. Due to the high impedance control circuit, an exclusive terminal for high impedance control is not necessary.Type: ApplicationFiled: January 16, 2003Publication date: September 18, 2003Applicant: FUJITSU LIMITEDInventors: Kenji Nagai, Hirokazu Nagashima