Patents by Inventor Hirokazu Yoshino
Hirokazu Yoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11058006Abstract: A component-embedded substrate includes: a buildup layer including an insulating resin layer and a conductor layer; a cavity that is formed in the buildup layer; an electronic component that is mounted on a bottom face of the cavity through an adhesive layer; a pedestal that is disposed on the bottom face of the cavity so as to be opposed to four corners of the electronic component; and a filling resin layer that is filled into the cavity to cover the electronic component and the pedestal.Type: GrantFiled: April 2, 2020Date of Patent: July 6, 2021Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Hirokazu Yoshino
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Publication number: 20200329564Abstract: A component-embedded substrate includes: a buildup layer including an insulating resin layer and a conductor layer; a cavity that is formed in the buildup layer; an electronic component that is mounted on a bottom face of the cavity through an adhesive layer; a pedestal that is disposed on the bottom face of the cavity so as to be opposed to four corners of the electronic component; and a filling resin layer that is filled into the cavity to cover the electronic component and the pedestal.Type: ApplicationFiled: April 2, 2020Publication date: October 15, 2020Inventor: Hirokazu Yoshino
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Patent number: 9899304Abstract: A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer. The first through hole includes a recess defined in an upper surface of the protective insulation layer by a curved wall surface and an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess. The opening is smaller than the recess in a plan view.Type: GrantFiled: December 16, 2016Date of Patent: February 20, 2018Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Imafuji, Keiji Yoshizawa, Hirokazu Yoshino, Kenta Uchiyama
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Publication number: 20170186677Abstract: A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer. The first through hole includes a recess defined in an upper surface of the protective insulation layer by a curved wall surface and an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess. The opening is smaller than the recess in a plan view.Type: ApplicationFiled: December 16, 2016Publication date: June 29, 2017Inventors: KEI IMAFUJI, KEIJI YOSHIZAWA, HIROKAZU YOSHINO, KENTA UCHIYAMA
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Patent number: 8581421Abstract: According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.Type: GrantFiled: December 16, 2011Date of Patent: November 12, 2013Assignee: Shinko Electric Industries Co., Ltd.Inventors: Noriyoshi Shimizu, Akio Rokugawa, Hirokazu Yoshino
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Publication number: 20120153457Abstract: According to one embodiment, there is provided a semiconductor package manufacturing method utilizing a support body in which a first layer is stacked on a second layer, the method including: a first step of forming an opening in the first layer to expose the second layer therethrough; a second step of arranging a semiconductor chip on the second layer through the opening; a third step of forming a resin portion on the first layer to cover the semiconductor chip; and a fourth step of forming a wiring structure on the resin portion so as to be electrically connected to the semiconductor chip.Type: ApplicationFiled: December 16, 2011Publication date: June 21, 2012Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Noriyoshi Shimizu, Akio Rokugawa, Hirokazu Yoshino
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Publication number: 20070220902Abstract: A thermoelectric converter comprises a thermoelectric element assembly that includes a plurality of P-type thermoelectric elements and a plurality of N-type thermoelectric elements which are arranged in a predetermined arrangement pattern; and a heat-exchange element assembly provided with a plurality of heat exchange elements and a retaining plate retaining the plurality of the heat exchange elements, the plurality of the heat exchange elements being retained in a predetermined arrangement condition corresponding to a arrangement condition of the thermoelectric elements. Then, a plurality of joining sites between the thermoelectric element assembly and the heat-exchange element assembly are all together joined by joining members in a state in which the thermoelectric element assembly and the heat-exchange element assembly are stacked on each other.Type: ApplicationFiled: May 31, 2005Publication date: September 27, 2007Applicant: DENSO CORPORATIONInventors: Akio Matsuoka, Isao Kuroyanagi, Takashi Yamamoto, Yukinori Hatano, Makoto Uto, Yasuhiko Niimi, Hirokazu Yoshino, Fumiaki Nakamura, Satoshi Mizutani, Jiro Ebihara
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Publication number: 20060219286Abstract: A thermoelectric transducer includes a thermoelectric device assembly and a pair of heat exchanging member assemblies arranged at both sides of the thermoelectric device assembly. The thermoelectric device assembly includes a plurality of P-type thermoelectric devices, a plurality of N-type thermoelectric devices, a first holding plate for holding the thermoelectric devices, and a plurality of electrode members for electrically connecting the thermoelectric devices. Each of the heat exchanging member assemblies includes a plurality of heat exchanging members provided in correspondence with the plurality of electrode members, and a second holding plate located for holding the plurality of heat exchanging members. Each of the plurality of electrode members has an outer periphery that contacts one surface of the second holding plate in a state where the electrode member is connected to the heat exchanging member.Type: ApplicationFiled: March 31, 2006Publication date: October 5, 2006Applicant: DENSO CorporationInventors: Isao Kuroyanagi, Akio Matsuoka, Takashi Yamamoto, Makoto Uto, Yukinori Hatano, Hirokazu Yoshino, Fumiaki Nakamura
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Patent number: 5492394Abstract: The invention is directed to a hydraulic braking system having a master cylinder (10) in which a first piston and a second piston are slidably disposed to define a first pressure chamber (11) and a second pressure chamber (12). A valve device (24) is provided between the first pressure chamber and a reservoir (20). A first pressure control device (30, 31) is provided between the first pressure chamber and wheel cylinders (38, 39), and a second pressure control device (32, 33) is provided between the second pressure chamber and wheel cylinders (40, 41). A pump (27) is provided in a passage connecting the reservoir and the first pressure control device, and driven to supply a brake pressure from the former to the latter.Type: GrantFiled: December 21, 1994Date of Patent: February 20, 1996Assignee: Aisin Seiki Kabushiki KaishaInventors: Akihito Kusano, Toru Watanabe, Hiroshi Toda, Hirokazu Yoshino
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Patent number: 5390051Abstract: A mirror angle adjustment structure is provided for an optical system, such as a laser scanning unit. The structure comprises a support projection projected from a mirror support member at a position corresponding to an end along the lengthwise direction of the mirror, an adjustment screw member disposed at the other end of the mirror corresponding to another end across the mirror and passed through and threaded with the mirror support member from the side where the mirror is disposed, and an urging mechanism, such as a leaf spring, for urging the mirror towards the support projection and the adjustment screw member.Type: GrantFiled: April 23, 1992Date of Patent: February 14, 1995Assignee: Asahi Kogaku Kogyo Kabushiki KaishaInventors: Taizo Saito, Morio Takizawa, Hirokazu Yoshino
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Patent number: 4249211Abstract: An image display apparatus has an: image signal receiver for simultaneously receiving two different image signals, a first image signal and a second image signal; a memory for writing therein the second image signal; controlling means for controlling the writing position, writing frequency, writing sequence, reading-out sequence, reading-out frequency and start-timing of reading-out of the second image signal; a display for displaying full picture information or partial picture information of the second image signal a part of a displayed picture of the first image signal by selectively reading-out the second image signal under the control of the controller; and zoom-up device for stepwisely or continuously varying the writing position and reading-out position of the second image signal controlled by the controller so as to zoomwisely display the full or partial picture of the second image signal on the picture of the first image signal.Type: GrantFiled: February 5, 1979Date of Patent: February 3, 1981Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takaaki Baba, Teruo Kitani, Masao Nakazawa, Hirokazu Yoshino, Tatsuo Fujita, Eiichi Tsuboka
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Patent number: 4238773Abstract: A television receiver is disclosed, which receives two television signals and compresses a time axis of one of the television signals and inserts the compressed signal to a portion of the other television signal to display both signals on the same screen. A signal indicating a boundary of the two images is produced from a synchronizing signal derived from one of the two received television signals and the boundary indicating signal is superimposed on one or both of a brightness signal and a chrominance signal to display the boundary.Type: GrantFiled: December 28, 1978Date of Patent: December 9, 1980Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Eiichi Tsuboka, Takeji Kimura, Hirokazu Yoshino, Tatuo Fujita, Masao Nakazawa
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Patent number: 3935536Abstract: A ghost signal cancellation system for cancelling ghost signals caused, for example, by reflection in a transmission line of television signals transmitted from a television transmitting station. This system is particularly suited for incorporation in a television receiver to improve the picture quality of a reproduced picture.Type: GrantFiled: March 14, 1973Date of Patent: January 27, 1976Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeji Kimura, Tomio Oyama, Haruyasu Yamada, Shuzi Harada, Hirokazu Yoshino, Eiichi Tsuboka