Patents by Inventor Hiroki Fujii
Hiroki Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9977733Abstract: When a data utilization ratio R which is a utilization ratio of sectors in one page is not lower than a threshold value Rth1 and when write data is not frequently-rewritten data, a flash memory is controlled such that the write data is stored into the flash memory. When the data utilization ratio R which is the utilization ratio of sectors in one page is lower than the threshold value Rth1 or when the write data is frequently-rewritten data although the data utilization ratio R is not lower than the threshold value Rth1, a ReRAM is controlled such that the write data is stored into the ReRAM. This suppresses deterioration of the flash memory.Type: GrantFiled: March 30, 2012Date of Patent: May 22, 2018Assignee: THE UNIVERSITY OF TOKYOInventors: Ken Takeuchi, Kousuke Miyaji, Koh Johguchi, Hiroki Fujii
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Publication number: 20180102431Abstract: A semiconductor device including an isolation insulating film having a first thickness that is located between a drain region and a source region; a gate electrode formed over a region located between the isolation insulating film and the source region and that includes a part serving as a channel; an interlayer insulating film formed so as to cover the gate electrode; and a contact plug formed to reach the inside of the isolation insulating film while penetrating the interlayer insulating film, wherein the contact plug includes a buried part that is formed from the surface of the isolation insulating film up to a depth corresponding to a second thickness thinner than the first thickness.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Applicant: Renesas Electronics CorporationInventors: Takahiro MORI, Hiroki FUJII
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Patent number: 9859416Abstract: An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor. In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.Type: GrantFiled: June 3, 2016Date of Patent: January 2, 2018Assignee: Renesas Electronics CorporationInventors: Takahiro Mori, Hiroki Fujii
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Publication number: 20170365711Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.Type: ApplicationFiled: September 1, 2017Publication date: December 21, 2017Inventor: Hiroki Fujii
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Publication number: 20170287912Abstract: A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation region defined by an element isolation insulating film, and a substrate contact portion. The substrate contact portion is formed in a region of a semiconductor substrate that is positioned between the high voltage NMOS transistor formation region and the element isolation insulating film so as to reach from the main surface side to a position deeper than the bottom of the element isolation insulating film. The substrate contact portion is in contact with the semiconductor substrate from a depth over a depth.Type: ApplicationFiled: March 20, 2017Publication date: October 5, 2017Applicant: Renesas Electronics CorporationInventors: Shigeo TOKUMITSU, Hiroki FUJII
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Patent number: 9753092Abstract: A battery monitoring system of flying capacitor type detects voltage difference between adjacent unit cells connected in series in battery pack. The system has the unit cells, an open and close section, a first and second capacitor, a first and second switching section, an ADC, and a microcomputer. The microcomputer instructs the open and close section to charge each of the first and second capacitors with each unit cell. After the first and second capacitors have been charged by the corresponding unit cells, the microcomputer instructs the first switching section to connect the first capacitor and the second capacitor in a reverse-polarity series connection. The microcomputer allows the second switching section to supply a voltage at both ends of the first and second capacitors connected in the reverse-polarity series connection, i.e. a voltage difference between the unit cells, to the ADC. The ADC supplies a conversion result to the microcomputer.Type: GrantFiled: August 27, 2015Date of Patent: September 5, 2017Assignee: DENSO CORPORATIONInventor: Hiroki Fujii
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Patent number: 9755069Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.Type: GrantFiled: April 28, 2016Date of Patent: September 5, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiroki Fujii
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Patent number: 9707851Abstract: A power supply system is provided. For storage devices, upper limit powers are determined. A control unit includes a target power acquiring section which acquires power requested by an object or power supplied by a charging apparatus as target power of charge/discharge performed by storage devices. A residual capacity acquiring section acquires residual capacities of the storage devices. A first target power allocating section allocates the target power to the storage devices as charge/discharge powers based on the residual capacities. A determining section determines whether or not the allocated charge/discharge powers exceed the upper limit powers of the storage devices. A second target power allocating section reallocates the target power to the storage devices so that the allocated charge/discharge powers do not exceed the upper limit powers, when the determining section determines that any of the charge/discharge powers has exceeded the upper limit power of the related storage device.Type: GrantFiled: March 6, 2015Date of Patent: July 18, 2017Assignee: DENSO CORPORATIONInventors: Tomomi Nonomura, Hiroki Fujii
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Patent number: 9708510Abstract: A pressure-sensitive adhesive composition includes 100 parts by mass of a rubber component containing 40 to 93 mass % of a butyl rubber and 7 to 60 mass % of a polyisobutylene and 82 to 128 parts by mass of a softener having a kinetic viscosity at 40° C. of 100 to 9,000 mm2/s.Type: GrantFiled: March 5, 2013Date of Patent: July 18, 2017Assignee: NITTO DENKO CORPORATIONInventors: Youhei Hayashi, Hiroki Fujii, Tetsuro Taga, Shinichiro Kose, Yoshiaki Mitsuoka, Akihiro Kiriyama
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Publication number: 20170191384Abstract: An object is to provide a roller lifter which can maintain a proper dimensional accuracy of an outer diameter. A shaft (25) rotatably supporting a roller (30) is inserted through a pair of opposed portions (21) and swaged to be fixed. A cylindrical portion (61) is disposed to be fixed at a relative position to the opposed portions (21). Upon rotation of a cam (90), the cylindrical portion (61) is reciprocated via the roller (30). The roller lifter (10) includes a first member (20) in which the shaft (25) is swaged to be fixed to the opposed portions (21) and a second member (60) separate from the first member (20) and couplable via a coupling member to the first member (20). The second member (60) includes at least the cylindrical portion (61).Type: ApplicationFiled: May 13, 2015Publication date: July 6, 2017Applicant: OTICS CORPORATIONInventors: Hideki OKA, Hiroki FUJII, Naoyuki YAMANE
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Publication number: 20170179221Abstract: A semiconductor device according to one embodiment of the present invention comprises: a semiconductor substrate having a main surface; a noise source element formed at the main surface of the semiconductor substrate; a protection target element formed at the main surface of the semiconductor substrate; an n type region disposed between the noise source element and the protection target element; and a p type region disposed between the noise source element and the protection target element and electrically connected to the n type region. The n type region and the p type region are adjacent to each other on the main surface of the semiconductor substrate in a direction intersecting a direction from the noise source element toward the protection target element.Type: ApplicationFiled: December 15, 2016Publication date: June 22, 2017Inventor: Hiroki FUJII
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Publication number: 20170025532Abstract: An object of the present invention is to further improve electric characteristics such as ON-resistance or an ON-breakdown voltage in a semiconductor device having a lateral MOS transistor. In a semiconductor device having a lateral MOS transistor, a buried electrode is formed at a part of an isolation insulating film located between a drain region and a gate electrode. The buried electrode includes a buried part. The buried part is formed from the surface of the isolation insulating film up to a depth corresponding to a thickness thinner than that of the isolation insulating film. The buried electrode is electrically coupled to the drain region.Type: ApplicationFiled: June 3, 2016Publication date: January 26, 2017Applicant: Renesas Electronics CorporationInventors: Takahiro MORI, Hiroki FUJII
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Patent number: 9422834Abstract: A roller lifter for internal combustion engines is provided, which has higher rigidity of the lifter body, prevents cocking in the cylinder, and can achieve a size reduction. The roller lifter includes a cylindrical lifter body having a sliding surface on an outer circumferential surface thereof and a roller rotatably attached to the lifter body via an axial support pin and making contact with a rotating cam lobe. The lifter body includes a pair of support portions supporting the axial support pin. The axial support pin is mechanically fastened to the pair of support portions, with both ends thereof inserted in support holes formed in the support portions. The lifter body includes an anti-rotation retainer extending radially outward from the sliding surface. The sliding surface is formed on both front and rear sides in the sliding direction of the anti-rotation retainer.Type: GrantFiled: June 11, 2013Date of Patent: August 23, 2016Assignee: OTICS CorporationInventors: Hiroki Fujii, Kiyoshi Masegi
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Publication number: 20160240664Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.Type: ApplicationFiled: April 28, 2016Publication date: August 18, 2016Inventor: Hiroki Fujii
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Patent number: 9356138Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.Type: GrantFiled: February 11, 2015Date of Patent: May 31, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Hiroki Fujii
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Publication number: 20160091572Abstract: A battery monitoring system of flying capacitor type detects voltage difference between adjacent unit cells connected in series in battery pack. The system has the unit cells, an open and close section, a first and second capacitor, a first and second switching section, an ADC, and a microcomputer. The microcomputer instructs the open and close section to charge each of the first and second capacitors with each unit cell. After the first and second capacitors have been charged by the corresponding unit cells, the microcomputer instructs the first switching section to connect the first capacitor and the second capacitor in a reverse-polarity series connection. The microcomputer allows the second switching section to supply a voltage at both ends of the first and second capacitors connected in the reverse-polarity series connection, i.e. a voltage difference between the unit cells, to the ADC. The ADC supplies a conversion result to the microcomputer.Type: ApplicationFiled: August 27, 2015Publication date: March 31, 2016Inventor: Hiroki FUJII
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Patent number: 9283606Abstract: A method of manufacturing a supporting structure includes disposing a supported member between a pair of opposed support walls, the support walls and the supported member having shaft holes formed coaxially through the support walls and the supported member respectively, inserting a shaft member through the shaft holes in the disposed state, the shaft member having two ends each having a peripheral portion circumferentially divided into a plurality of swaging portions continuous without discontinuity and swaging the swaging portions sequentially such that regions of the shaft member corresponding to the respective swaging portions are fixed in the shaft holes. The swaging portions include first swaging portions and second swaging portions, both of which are disposed so as to be paired at both radial sides of the shaft holes, respectively. A larger swage load is applied to each first swaging portion than to each second swaging portion.Type: GrantFiled: January 14, 2013Date of Patent: March 15, 2016Assignee: OTICS CORPORATIONInventors: Hideki Oka, Hiroki Fujii, Kazunori Kawahara, Haruyasu Tanaka
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Patent number: 9206711Abstract: A lash adjuster includes a body, a plunger inserted into the body and having a bottom wall with a valve hole and a peripheral wall having an oil passage hole, and a partitioning member. The partitioning member is inserted into the plunger and has an oil passage end located above the oil passage hole in an inserted state. The partitioning member has a recess defining an oil passage together with the peripheral wall. The partitioning member defines a low-pressure chamber reserving hydraulic fluid and has, together with the recess, a press-fit portion abutting against an inner periphery of the peripheral wall when the partitioning member is inserted into the plunger. Consequently, the partitioning member has a deformed cross-sectional shape except for a circular shape when cut at a same height as the oil passage hole. The partitioning member has a same cross-sectional shape over its entire height.Type: GrantFiled: February 7, 2014Date of Patent: December 8, 2015Assignee: OTICS CORPORATIONInventors: Hiroki Fujii, Kimihiko Todo
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Publication number: 20150251547Abstract: A power supply system is provided. For storage devices, upper limit powers are determined. A control unit includes a target power acquiring section which acquires power requested by an object or power supplied by a charging apparatus as target power of charge/discharge performed by storage devices. A residual capacity acquiring section acquires residual capacities of the storage devices. A first target power allocating section allocates the target power to the storage devices as charge/discharge powers based on the residual capacities. A determining section determines whether or not the allocated charge/discharge powers exceed the upper limit powers of the storage devices. A second target power allocating section reallocates the target power to the storage devices so that the allocated charge/discharge powers do not exceed the upper limit powers, when the determining section determines that any of the charge/discharge powers has exceeded the upper limit power of the related storage device.Type: ApplicationFiled: March 6, 2015Publication date: September 10, 2015Inventors: Tomomi NONOMURA, Hiroki FUJII
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Publication number: 20150243777Abstract: There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.Type: ApplicationFiled: February 11, 2015Publication date: August 27, 2015Inventor: Hiroki Fujii