Patents by Inventor Hiroki Ueno

Hiroki Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050110516
    Abstract: The present invention provides a semiconductor device that can shorten the initialization cycle of impedance matching of interface buffers and reduce as much as possible affects on other circuits at the time of fine control thereafter. The semiconductor device (1) includes interface buffers (18a to 18c) whose internal impedances are controlled by impedance control data and an impedance control circuit (35) that generates the impedance control data. The impedance control circuit includes a first impedance control mode that initially generates the impedance control data by a binary search and comparison operation resulting from predetermined impedance control steps and sets the impedance control data in the interface buffers, and a second impedance control mode that updates the impedance control data set in the interface buffers by a sequential comparison operation resulting from the predetermined impedance control steps.
    Type: Application
    Filed: October 21, 2004
    Publication date: May 26, 2005
    Inventor: Hiroki Ueno
  • Publication number: 20050104620
    Abstract: A semiconductor device is easy for high accuracy impedance matching against differences in impedance of a transmission line and a package wire. A semiconductor chip having external output buffers and a packaging circuit are included. Each external output buffer has a first output portion whose internal impedance is adjusted commonly with other external output buffers in accordance with impedance control data and a second output portion whose internal impedance is adjusted independently of other external output buffers. Both of the first and second output portions are connected in parallel to a common output terminal. Common adjustment by the first output portion can cope with impedance of the transmission line and individual adjustment by the second output portion can cope with a difference of package wires.
    Type: Application
    Filed: November 9, 2004
    Publication date: May 19, 2005
    Inventor: Hiroki Ueno
  • Patent number: 6856559
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: February 15, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20040027896
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: August 11, 2003
    Publication date: February 12, 2004
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co. , Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Patent number: 6625070
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: September 23, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Publication number: 20020075732
    Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.
    Type: Application
    Filed: December 11, 2001
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd
    Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
  • Patent number: 6090970
    Abstract: A method for producing alkylated cyanoacetylurea from an easily obtainable starting material. An industrially available cyanoacetylurea and a carbonyl compound are reacted in a polar solvent under reducing conditions to alkylate cyanoacetylurea In addition, a reaction of cyanoacetylurea and acetone under reducing conditions affords isopropylation of cyanoacetylurea.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: July 18, 2000
    Assignee: Sumika Fine Chemicals Co., Ltd.
    Inventors: Yutaka Otani, Hiroki Ueno, Michio Matsuda, Yoshiyuki Imamiya
  • Patent number: 5914399
    Abstract: A method for producing 5-isopropyluracil at a high yield in a short time, wherein N-(2-cyano-3-methylbutanoyl)urea is reduced in a 10-15% aqueous sulfuric acid solution in the presence of palladium carbon at 30-45.degree. C., heated for ring closure reaction and added to a 50-70% aqueous sulfuric acid solution to give 5-isopropyluracil having a high purity.
    Type: Grant
    Filed: October 20, 1998
    Date of Patent: June 22, 1999
    Assignee: Sumika Fine Chemicals Co., Ltd.
    Inventors: Hiroki Ueno, Michio Matsuda, Susumu Nishizawa