Patents by Inventor Hiroki Yabe
Hiroki Yabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11405039Abstract: A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first NMOS transistor and a first PMOS transistor in series with a first input node and a negative amplified voltage, and the second leg includes a second NMOS transistor and a second PMOS transistor in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.Type: GrantFiled: June 2, 2021Date of Patent: August 2, 2022Assignee: SANDISK TECHNOLOGIES LLCInventor: Hiroki Yabe
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Publication number: 20220208270Abstract: A method for programming three page user data in a memory array of a non-volatile memory system, comprising converting each three-bit value data pattern of the user data into a representative pair of two-bit data values, simultaneously programming two single-state memory cells with a first of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a first common word line of two memory cell strings, and simultaneously programming two single-state memory cells with a second of the pair of representative two-bit data values, wherein the two single-state memory cells are located along a second common word line of the two memory cell strings.Type: ApplicationFiled: December 29, 2020Publication date: June 30, 2022Applicant: SanDisk Technologies LLCInventors: Keiji Nose, Hiroki Yabe, Masahiro Kano, Yuki Fujita
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Patent number: 11348649Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: June 23, 2020Date of Patent: May 31, 2022Assignee: SanDisk Technologies LLCInventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
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Patent number: 11336283Abstract: A level shifting circuit includes negative voltage shifting circuitry including a first leg and a second leg. The first leg includes a first plurality of NMOS transistors in series with a first input node and a negative amplified voltage, and the second leg includes a second plurality of NMOS transistors in series with a second input node and the negative amplified voltage. The level shifting circuit further includes positive voltage shifting circuitry including a first plurality of high voltage transistors in series with a positive amplified voltage and an output node of the level shifting circuit, and a second plurality of high voltage transistors in series with a first intermediate node of the first leg of the negative voltage shifting circuitry and the output node of the level shifting circuit. The level shifting circuitry further includes input circuitry including a plurality of inverters.Type: GrantFiled: May 21, 2021Date of Patent: May 17, 2022Assignee: SANDISK TECHNOLOGIES LLCInventor: Hiroki Yabe
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Patent number: 11250920Abstract: A storage device for verifying whether memory cells have been programmed. The storage device may be configured to use a verification technique, that is part of a set of verification techniques, to verify data states of a set of memory cells of a selected word line. The one or more verification techniques may be utilized based on an iteration of the verify operation that is to be performed. The storage device may be further configured to perform, using the verification technique, a next iteration of the program-verify operation to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next-iteration of the program-verify operation are to be repeated until the set of memory cells have been verified.Type: GrantFiled: June 30, 2020Date of Patent: February 15, 2022Assignee: SanDisk Technologies LLCInventor: Hiroki Yabe
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Publication number: 20210407604Abstract: A storage device for verifying whether memory cells have been programmed. The storage device may be configured to use a verification technique, that is part of a set of verification techniques, to verify data states of a set of memory cells of a selected word line. The one or more verification techniques may be utilized based on an iteration of the verify operation that is to be performed. The storage device may be further configured to perform, using the verification technique, a next iteration of the program-verify operation to verify whether one or more memory cells have been programmed. Using the verification technique and performing the next-iteration of the program-verify operation are to be repeated until the set of memory cells have been verified.Type: ApplicationFiled: June 30, 2020Publication date: December 30, 2021Applicant: SanDisk Technologies LLCInventor: Hiroki Yabe
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Publication number: 20210359325Abstract: A redox flow battery includes a negative electrode; a positive electrode; a first liquid which contains a first nonaqueous solvent, a first redox species, and metal ions and which is in contact with the negative electrode; a second liquid which contains a second nonaqueous solvent and which is in contact with the positive electrode; and a metal ion-conducting membrane disposed between the first liquid and the second liquid. The metal ion-conducting membrane contains a plurality of inorganic particles and a binder which contains an organic polymer and which binds the inorganic particles together.Type: ApplicationFiled: July 27, 2021Publication date: November 18, 2021Inventors: HONAMI SAKO, MASAHISA FUJIMOTO, HIROKI YABE, SHUJI ITO
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Patent number: 11177277Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.Type: GrantFiled: November 6, 2019Date of Patent: November 16, 2021Assignee: SanDisk Technologies LLCInventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
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Patent number: 11158384Abstract: An apparatus is provided that includes a plurality of NAND strings having a common set of word lines. Each NAND string includes data memory cells for data storage and dummy memory cells connected in series with the data memory cells. A first group of NAND strings includes dummy memory cells with a first pattern of threshold voltages and a second group of NAND strings includes dummy memory cells with a second pattern of threshold voltages for separate isolation of data memory cells of the first and second groups of NAND strings from corresponding bit lines.Type: GrantFiled: May 20, 2020Date of Patent: October 26, 2021Assignee: SanDisk Technologies LLCInventor: Hiroki Yabe
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Publication number: 20210319833Abstract: An apparatus is provided that includes a plurality of non-volatile memory cells, a plurality of bit lines, a plurality of memory holes, and a control circuit. The plurality of memory holes each include a corresponding one of the memory cells. Each memory hole is associated with and coupled to a corresponding one of the bit lines. The control circuit is configured to read the memory cells in four separate read intervals.Type: ApplicationFiled: April 10, 2020Publication date: October 14, 2021Applicant: SanDisk Technologies LLCInventor: Hiroki Yabe
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Patent number: 11087800Abstract: A sense amplifier architecture is presented that can reduce sensing times by being able to sense smaller voltage swings between an ON memory cell and an OFF memory cell. The sense amplifier includes a sensing capacitor that, on one side, is connectable to multiple bit lines and, on the other side, to a main sense amplifier section. The main section includes a latch formed of a pair of inverters that has an input connected to the capacitor and an output that is connected to the other side of the capacitor by a third inverter. To pre-charge the latch, the input and output nodes are shorted and then the capacitor is connected to discharge the capacitor through a selected memory cell based on whether it is ON or OFF. A programming data latch for each bit line can bias the bit line to either a program enable or program inhibit level.Type: GrantFiled: April 10, 2020Date of Patent: August 10, 2021Assignee: SanDisk Technologies LLCInventor: Hiroki Yabe
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Patent number: 11081192Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.Type: GrantFiled: October 30, 2019Date of Patent: August 3, 2021Assignee: SanDiskTechnologies LLCInventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
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Patent number: 11081167Abstract: Systems and methods for reducing the energy per bit of memory cell sensing operations, such as memory read operations, by dynamically adjusting the body effect of data latch transistors during the sensing operations are described. A significant component of the energy required to perform the memory cell sensing operations may correspond with the parasitic currents through low threshold voltage (VT) transistors of data latches within sense amplifier circuits. In order to reduce the energy per bit of the memory cell sensing operations while using a reduced supply voltage for the data latches, the body effect of a select number of the low VT transistors within the data latches may be dynamically adjusted such that the body effect is minimized or nonexistent during the latching of new data into the data latches and then increased after the new data has been latched within the data latches.Type: GrantFiled: June 26, 2020Date of Patent: August 3, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Hiroki Yabe, Koichiro Hayashi
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Publication number: 20210142858Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.Type: ApplicationFiled: November 13, 2019Publication date: May 13, 2021Applicant: SanDisk Technologies LLCInventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
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Patent number: 11004518Abstract: Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.Type: GrantFiled: June 28, 2019Date of Patent: May 11, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Kiyohiko Sakakibara, Hiroki Yabe, Ken Oowada, Masaaki Higashitani
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Publication number: 20210134828Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.Type: ApplicationFiled: November 6, 2019Publication date: May 6, 2021Applicant: SanDisk Technologies LLCInventors: Naoki Ookuma, Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Toru Miwa
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Publication number: 20210134375Abstract: A non-volatile memory device comprising a memory cell region having a plurality of co-planar memory cell planes arranged in a plane parallel to a semiconductor substrate, with each memory cell plane comprising a plurality of sub-planes disposed adjacent one another along an axis that is parallel to the substrate. Further, each memory cell plane comprises a plurality of sense amplifier regions arranged along the axis in an alternating pattern with the sub-planes such that adjacent to each sub-plane is a sense amplifier region and each sense amplifier region is operable with respect to at least a fraction of the bit lines of the two sub-planes immediately adjacent the sense amplifier region.Type: ApplicationFiled: October 30, 2019Publication date: May 6, 2021Applicant: SanDisk Technologies LLCInventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
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Patent number: 10984877Abstract: An apparatus and method for a multi-state verify of a memory array are provided. A sense circuit of a memory device is connected to a bit line of the memory array. The sense circuit includes a first voltage clamp, a second voltage clamp, and a program data latch disposed on the bit line. The first and second voltage clamps are biased to first and second voltages, respectively, where the first voltage is lower than the second voltage. When a high bias is applied to the program data latch, the program data latch is in an OFF state, and the first voltage clamp limits the bias on the bit line to the first voltage. When a low bias is applied to the program data latch, the program data latch is in an ON state, and the second voltage clamp limits the bias on the bit line to the second voltage.Type: GrantFiled: December 17, 2019Date of Patent: April 20, 2021Assignee: SanDiskTechnologies LLCInventors: Jongyeon Kim, Hiroki Yabe, Kou Tei, Chia-Kai Chou, Ohwon Kwon
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Patent number: 10984874Abstract: A random access memory is provided including a plane structure comprising a plurality of sense amplifiers, each including a local data latch, a pair of local busses connected to each of the data latches, a differential data bus, and a pair of redrivers connected between the pair of local busses and the differential data bus.Type: GrantFiled: November 13, 2019Date of Patent: April 20, 2021Assignee: SanDisk Technologies LLCInventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Naoki Ookuma, Toru Miwa
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Patent number: 10964390Abstract: An apparatus and method of skip coding user data is provided. According to skip coding, for each cell in which an upper page is 0, data is stored in a half page. For each portion of data in which the upper page is 1, data is not stored in the half page. Thus, cells of a NAND memory may each store 3.5 bits, in one of twelve available states.Type: GrantFiled: December 10, 2019Date of Patent: March 30, 2021Assignee: Western Digital Technologies, Inc.Inventor: Hiroki Yabe