Patents by Inventor Hiroki Yamashita

Hiroki Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170345838
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.
    Type: Application
    Filed: August 16, 2017
    Publication date: November 30, 2017
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroki YAMASHITA
  • Publication number: 20170301919
    Abstract: The present invention provides a positive-electrode active material for a lithium-ion secondary cell or a sodium-ion secondary cell, which can effectively exhibit more excellent charge/discharge characteristics; and a method for manufacturing the positive-electrode active material. Namely, the present invention relates to a positive-electrode active material for a secondary cell comprising an oxide represented by formula (A): LiFeaMnbMcPO4, formula (B): LiFeaMnbMcSiO4, or formula (C): NaFegMnhQiPO4; and carbon derived from a cellulose nanofiber supported thereon.
    Type: Application
    Filed: September 15, 2015
    Publication date: October 19, 2017
    Applicant: TAIHEIYO CEMENT CORPORATION
    Inventors: Hiroki YAMASHITA, Tomoki HATSUMORI, Takaaki OGAMI
  • Patent number: 9786680
    Abstract: A semiconductor device includes: a semiconductor substrate, a first portion and a second portion of an upper layer portion of the semiconductor substrate being conductive; an insulating member electrically isolating the first portion from the second portion; a first stacked body provided in a region directly above the second portion, the first stacked body including first insulating films and electrode films stacked alternately; a semiconductor pillar provided inside the first stacked body and extending in a stacking direction; a charge storage film provided between the semiconductor pillar and the electrode films; a second stacked body provided in a region directly above the first portion, the second stacked body including second insulating films and third insulating films stacked alternately; and two first conductive pillars provided inside the second stacked body extending in the stacking direction, lower ends thereof being connected to the first portion.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: October 10, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shun Shimizu, Hiroki Yamashita
  • Patent number: 9773797
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: September 26, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroki Yamashita
  • Publication number: 20170263632
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, columnar portions, and first and second interconnection portions. The stacked body includes insulating layers and electrode layers alternately stacked one layer by one layer on the substrate. The columnar portions are provided between the first and second interconnection portions and include a first row having a first columnar portion and a second row having a second columnar portion, the first columnar portion being positioned closest to the first interconnection portion, and the second columnar portion being positioned closest to the second interconnection portion. A distance between the first interconnection portion and the first columnar portion is smaller than a distance between the second interconnection portion and the second columnar portion, and the distance between the second interconnection portion and the second columnar portion is greater than 20 nanometers.
    Type: Application
    Filed: September 12, 2016
    Publication date: September 14, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroki YAMASHITA, Yoshiaki FUKUZUMI
  • Publication number: 20170263612
    Abstract: A semiconductor memory device includes a plurality of first electrode layers stacked in a first direction; a semiconductor layer extending in the first direction in the plurality of first electrode layers; a first insulating layer extending in the first direction along the semiconductor layer between the semiconductor layer and each of the plurality of first electrode layers; a second insulating layer covering the periphery of the plurality of first electrode layers; a resistive body provided on the second insulating layer; and a third insulating layer provided between the resistive body and the second insulating layer, the third insulating layer including the same material as the material of the first insulating layer.
    Type: Application
    Filed: September 16, 2016
    Publication date: September 14, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroki YAMASHITA
  • Publication number: 20170243817
    Abstract: A semiconductor memory device includes a plurality of first electrode layers stacked; a second electrode layer provided on the first electrode layers; a third electrode layer arranged with the second electrode layers on the first electrode layers; a first insulating layer including a first layer provided between the second electrode layer and the third electrode layer, a second layer provided between the second electrode layer and the first layer, and a third layer provided between the third electrode layer and the first layer; a plurality of semiconductor layers extending through the first electrode layers in a stacked direction thereof, and disposed in an arrayed arrangement; and a charge storage portion positioned between one of the first electrode layers and one of the semiconductor layers.
    Type: Application
    Filed: July 15, 2016
    Publication date: August 24, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroki YAMASHITA
  • Patent number: 9739622
    Abstract: A system and method for selecting a path according to a plurality of selection conditions are disclosed, where a vehicle traveling history data stored in the plurality type of driving data recorder (DDR) databases established previously are analyzed, and then a plurality type of DDR databases are screened out by further referring to a plurality of type ratios provided by the user are screened out, and then a desired path is selected.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 22, 2017
    Assignee: YUAN ZE UNIVERSITY
    Inventors: Reijo Yamashita, Hiroki Yamashita, Hsiu-Hsen Yao
  • Patent number: 9704877
    Abstract: A semiconductor memory device includes a first stacked body, a semiconductor pillar extending the first direction and piercing the first stacked body, and a memory film disposed between the semiconductor pillar and the electrode film. The first stacked body includes a plurality of electrode films and a plurality of inter-layer insulating films stacked alternately along the first direction. The plurality of electrode films and the plurality of inter-layer insulating films extend in a second direction intersecting the first direction. Each of the electrode films includes a central portion and a peripheral portion. The central portion is disposed in a central part of the electrode film in a third direction, and includes silicon. The third direction intersects the first direction and the second direction. The peripheral portion is disposed on two sides of the central portion in the third direction, extends in the second direction and includes a metal.
    Type: Grant
    Filed: February 18, 2016
    Date of Patent: July 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroki Yamashita
  • Patent number: 9683195
    Abstract: The present invention aims to provide a viscosity index improver excellent in shear stability and having a low HTHS viscosity and a high viscosity index. The viscosity index improver of the present invention contains a (co)polymer (A) containing a polyolefin-based monomer as an essential monomer unit, and a base oil, wherein the absolute value of difference in solubility parameter between the (co)polymer (A) and the base oil is 0.8 to 2.0 (cal/cm3)1/2.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: June 20, 2017
    Assignee: SANYO CHEMICAL INDUSTRIES, LTD.
    Inventors: Shigekuni Nakada, Ayumu Sakaguchi, Takenori Tatsumi, Hiroki Yamashita
  • Publication number: 20170133393
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.
    Type: Application
    Filed: January 24, 2017
    Publication date: May 11, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroki YAMASHITA
  • Patent number: 9627391
    Abstract: According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroki Yamashita
  • Publication number: 20170077027
    Abstract: A semiconductor device includes: a semiconductor substrate, a first portion and a second portion of an upper layer portion of the semiconductor substrate being conductive; an insulating member electrically isolating the first portion from the second portion; a first stacked body provided in a region directly above the second portion, the first stacked body including first insulating films and electrode films stacked alternately; a semiconductor pillar provided inside the first stacked body and extending in a stacking direction; a charge storage film provided between the semiconductor pillar and the electrode films; a second stacked body provided in a region directly above the first portion, the second stacked body including second insulating films and third insulating films stacked alternately; and two first conductive pillars provided inside the second stacked body extending in the stacking direction, lower ends thereof being connected to the first portion.
    Type: Application
    Filed: January 28, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shun SHIMIZU, Hiroki YAMASHITA
  • Publication number: 20170062465
    Abstract: A semiconductor memory device includes a first stacked body, a semiconductor pillar extending the first direction and piercing the first stacked body, and a memory film disposed between the semiconductor pillar and the electrode film. The first stacked body includes a plurality of electrode films and a plurality of inter-layer insulating films stacked alternately along the first direction. The plurality of electrode films and the plurality of inter-layer insulating films extend in a second direction intersecting the first direction. Each of the electrode films includes a central portion and a peripheral portion. The central portion is disposed in a central part of the electrode film in a third direction, and includes silicon. The third direction intersects the first direction and the second direction. The peripheral portion is disposed on two sides of the central portion in the third direction, extends in the second direction and includes a metal.
    Type: Application
    Filed: February 18, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroki YAMASHITA
  • Publication number: 20170025350
    Abstract: A semiconductor memory device according to an embodiment includes: a pair of insulating members separated from each other, the pair of insulating members extending in a first direction; a plurality of electrode films and a plurality of inter-layer insulating films disposed between the pair of insulating members and stacked alternately along a second direction, the second direction intersecting the first direction; a plurality of semiconductor pillars extending in the second direction and piercing the plurality of electrode films and the plurality of inter-layer insulating films; and a charge storage film disposed between one of the semiconductor pillars and one of the electrode films. An end portion on one of the insulating members side of a first electrode film of the electrode films is thicker than a central portion of the first electrode film between the pair of insulating members.
    Type: Application
    Filed: February 1, 2016
    Publication date: January 26, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takamasa ITO, Hiroki YAMASHITA
  • Publication number: 20170009177
    Abstract: The present invention aims to provide a viscosity index improver excellent in shear stability and having a low HTHS viscosity and a high viscosity index. The viscosity index improver of the present invention contains a (co)polymer (A) containing a polyolefin-based monomer as an essential monomer unit, and a base oil, wherein the absolute value of difference in solubility parameter between the (co)polymer (A) and the base oil is 0.8 to 2.0 (cal/cm3)1/2.
    Type: Application
    Filed: February 25, 2015
    Publication date: January 12, 2017
    Applicant: SANYO CHEMICAL INDUSTRIES, LTD.
    Inventors: Shigekuni NAKADA, Ayumu SAKAGUCHI, Takenori TATSUMI, Hiroki YAMASHITA
  • Patent number: 9502455
    Abstract: A downsized, highly reliable optical apparatus is stably and easily manufactured with high productivity. The optical apparatus includes: an optical device having a principal surface including an optical unit; a transparent member disposed facing the optical unit; a semiconductor device disposed above a back surface of the optical device and electrically connected to the optical device, the back surface being opposite the principal surface; and a resin member provided in a region adjacent to the optical device and the semiconductor device above a surface of the transparent member, the surface of the transparent member facing the optical device.
    Type: Grant
    Filed: May 26, 2015
    Date of Patent: November 22, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Toshitaka Akahoshi, Hiroki Yamashita, Shigefumi Dohi
  • Publication number: 20160322410
    Abstract: An imaging device includes a solid-state image element and an encapsulation section. The solid-state image element has an imaging region. In the imaging region, the solid-state image element receives light which is transmitted through an imaging target placed on the imaging region. The encapsulation section is placed on a surface, on which the imaging region is formed, so as to enclose the imaging target. The solid-state image element is peelable from the encapsulation section to enable the solid-state image element to be reused.
    Type: Application
    Filed: July 10, 2016
    Publication date: November 3, 2016
    Inventors: HIROKI YAMASHITA, TAKESHI KAWABATA, SATORU WAGA, HIDETO MOTOMURA
  • Patent number: 9443793
    Abstract: A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 13, 2016
    Assignee: Panasonic Corporation
    Inventors: Hiroki Yamashita, Takashi Yui, Takeshi Kawabata, Kiyomi Hagihara, Kenji Yokoyama
  • Publication number: 20160162484
    Abstract: A system and method for selecting a path according to a plurality of selection conditions are disclosed, where a vehicle traveling history data stored in the plurality type of driving data recorder (DDR) databases established previously are analyzed, and then a plurality type of DDR databases are screened out by further referring to a plurality of type ratios provided by the user are screened out, and then a desired path is selected.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 9, 2016
    Inventors: REIJO YAMASHITA, HIROKI YAMASHITA, Hsiu-Hsen YAO