Patents by Inventor Hiromasa HIURA

Hiromasa HIURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IC chip layout for minimizing thermal expansion misalignment
    Patent number: 11177229
    Abstract: An integrated circuit (IC) chip comprises a plurality of pads and a plurality of bumps. The plurality of pads includes a first pad. The plurality of bumps is disposed on the plurality of pads. The plurality of bumps includes a first bump disposed on the first pad. The first bump as a width that is different than an exposed with of the first pad. The center of the first bump is not aligned with a center of the first pad.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: November 16, 2021
    Assignee: Synaptics Incorporated
    Inventors: Naoki Hasegawa, Shinya Suzuki, Hiromasa Hiura, Yuichi Nakagomi
  • INTEGRATED CIRCUIT CHIP LAYOUT
    Publication number: 20200321298
    Abstract: An integrated circuit (IC) chip comprises a plurality of pads and a plurality of bumps. The plurality of pads includes a first pad. The plurality of bumps is disposed on the plurality of pads. The plurality of bumps includes a first bump disposed on the first pad. The first bump as a width that is different than an exposed with of the first pad. The center of the first bump is not aligned with a center of the first pad.
    Type: Application
    Filed: April 2, 2020
    Publication date: October 8, 2020
    Inventors: Naoki HASEGAWA, Shinya SUZUKI, Hiromasa HIURA, Yuichi NAKAGOMI