Patents by Inventor Hiromasa Noda

Hiromasa Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190155763
    Abstract: Apparatuses and methods for transferring data from memory on a data path are described. An example apparatus includes: one or more data terminals; a plurality of memory banks, one of the plurality of memory banks being selected responsive, at least in part, to a bank address; and a data path including a plurality of data path routes and a plurality of switching buffers on the plurality of data path routes. The plurality of switching buffers are arranged such that one or more of the plurality of switching buffers are selected responsive, at least in part, to the bank address and activates one of the plurality of data path routes.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 23, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Hiromasa Noda
  • Patent number: 10198371
    Abstract: Apparatuses and methods for transferring data from memory on a data path are described. An example apparatus includes: one or more data terminals; a plurality of memory banks, one of the plurality of memory banks being selected responsive, at least in part, to a bank address; and a data path including a plurality of data path routes and a plurality of switching buffers on the plurality of data path routes. The plurality of switching buffers are arranged such that one or more of the plurality of switching buffers are selected responsive, at least in part, to the bank address and activates one of the plurality of data path routes.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 5, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Hiromasa Noda
  • Patent number: 10056154
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 21, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Patent number: 9934869
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: April 3, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Publication number: 20180075920
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Application
    Filed: August 3, 2017
    Publication date: March 15, 2018
    Applicant: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Patent number: 9824770
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: November 21, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Patent number: 9666307
    Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
    Type: Grant
    Filed: September 14, 2016
    Date of Patent: May 30, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Yoshinori Fujiwara, Kenji Yoshida, Minoru Someya, Hiromasa Noda
  • Publication number: 20170060789
    Abstract: Apparatuses and methods for transferring data from memory on a data path are described. An example apparatus includes: one or more data terminals; a plurality of memory banks, one of the plurality of memory banks being selected responsive, at least in part, to a bank address; and a data path including a plurality of data path routes and a plurality of switching buffers on the plurality of data path routes. The plurality of switching buffers are arranged such that one or more of the plurality of switching buffers are selected responsive, at least in part, to the bank address and activates one of the plurality of data path routes.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 2, 2017
    Inventor: Hiromasa Noda
  • Patent number: 9412432
    Abstract: A semiconductor storage device is provided with a memory cell array comprising a plurality of word lines including word lines that are adjacent to one another; and a TRR address conversion unit that selects the word line in response to the input of an address signal indicating a first value while in a first operation mode and selects the word line in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation. As a result, control of the target row refresh operation on the control device side is facilitated.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: August 9, 2016
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Seiji Narui, Hiromasa Noda, Chiaki Dono, Chikara Kondo, Masayuki Nakamura
  • Publication number: 20160042782
    Abstract: [Problem] To regenerate the charge of a memory cell having reduced information retention characteristics using a target row refresh operation. [Solution] A semiconductor storage device is provided with a memory cell array (11) comprising a plurality of word lines including word lines (WLI, WL2) that are adjacent to one another; and a TRR address conversion unit (53) that selects the word line (WL1) in response to the input of an address signal (IADD) indicating a first value while in a first operation mode and selects the word line (WL2) in response to the input of an address signal indicating a first value while in a target row refresh mode. Due to the fact that address conversion is performed on the semiconductor storage device side in the present invention, it is sufficient for a control device to output, for example, the address of a word line having a high access count to the semiconductor storage device during a target row refresh operation.
    Type: Application
    Filed: March 13, 2014
    Publication date: February 11, 2016
    Inventors: Seiji Narui, Hiromasa Noda, Chiaki Dono, Chikara Kondo, Masayuki Nakamura
  • Patent number: 9183949
    Abstract: A device includes a decoder, a selector, and a plurality of registers. The decoder is configured to generate a plurality of test signals. The selector is coupled to the decoder. The selector is configured to sequentially select a test signal from the plurality of test signals and to sequentially output the test signal selected. The plurality of registers is coupled in series to each other. The plurality of registers includes a first stage register. The first stage register is coupled to the selector to sequentially receive the test signal from the selector.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: November 10, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Hiromasa Noda, Toshio Ninomiya
  • Patent number: 9053821
    Abstract: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: June 9, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Yoshiro Riho, Hiromasa Noda, Kazuki Sakuma
  • Publication number: 20150071013
    Abstract: A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.
    Type: Application
    Filed: November 18, 2014
    Publication date: March 12, 2015
    Applicant: PS4 LUXCO S.A.R.L.
    Inventors: Takenori Sato, Yoji Idei, Hiromasa Noda
  • Patent number: 8891318
    Abstract: A semiconductor device includes: two level shift circuits having substantially the same circuit configuration; an input circuit that supplies complementary input signals to the level shift circuits, respectively; and an output circuit that converts complementary output signals output from the level shift circuits into in-phase signals and then short-circuits the in-phase signals. According to the present invention, the two level shift circuits having substantially the same circuit configuration are used, and the complementary output signals output from the level shift circuits are converted into in-phase signals before short-circuited. This avoids almost any occurrence of a through current due to a difference in operating speed between the level shift circuits.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: November 18, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Takenori Sato, Yoji Idei, Hiromasa Noda
  • Patent number: 8837242
    Abstract: A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 16, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Yoshiro Riho, Yoshio Mizukane, Hiromasa Noda
  • Publication number: 20140211582
    Abstract: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time.
    Type: Application
    Filed: April 2, 2014
    Publication date: July 31, 2014
    Inventors: Yoshiro Riho, Hiromasa Noda, Kazuki Sakuma
  • Patent number: 8737149
    Abstract: A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: May 27, 2014
    Inventors: Yoshiro Riho, Hiromasa Noda, Kazuki Sakuma
  • Publication number: 20140140155
    Abstract: A method includes selecting a word line included in one of a plurality of memory mats based on a row address, where each of the plurality of memory mats includes a plurality of word lines, a plurality of bit lines, and a redundant bit line, selecting one of the bit lines included in the selected memory mat based on a column address, selecting, by a column relief circuit, the redundant bit line in place of the one of the bit lines to be selected based on the column address, in response to the column address indicating a defective address, activating the column relief circuit when the row address is supplied in response to a first command, and inactivating the column relief circuit when the row address is supplied in response to a second command.
    Type: Application
    Filed: January 24, 2014
    Publication date: May 22, 2014
    Inventors: Yoshiro Riho, Yoshio Mizukane, Hiromasa Noda
  • Patent number: 8707114
    Abstract: A semiconductor device includes a decoder, a first register unit, and a second register unit. The decoder generates first and second register control signals in response to an external test code signal. The first register unit is coupled to the decoder. The first register unit receives the first register control signal from the decoder. The first register unit outputs in series a plurality of test signals in response to the first register control signal. The second register unit is coupled to the first register unit. The second register unit receives the first and second register control signals from the decoder. The second register unit receives in series the plurality of test signals from the first register unit in response to the first register control signal. The second register unit outputs in parallel the plurality of test signals in response to the second register control signal.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: April 22, 2014
    Inventor: Hiromasa Noda
  • Patent number: RE46202
    Abstract: There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell; a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: November 8, 2016
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda