Patents by Inventor Hiromasa Noda

Hiromasa Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110222362
    Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.
    Type: Application
    Filed: May 20, 2011
    Publication date: September 15, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiromasa NODA
  • Patent number: 8009505
    Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: August 30, 2011
    Assignee: Elpida Memory, Inc.
    Inventor: Hiromasa Noda
  • Patent number: 8000123
    Abstract: There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell; a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: August 16, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda
  • Patent number: 7969765
    Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
    Type: Grant
    Filed: October 8, 2008
    Date of Patent: June 28, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
  • Publication number: 20110131440
    Abstract: A semiconductor device includes an analog circuit with a first delay variation in response to a variation in a power supply potential, and a digital circuit with a second delay variation smaller than the first delay variation. The analog circuit is connected to a first power supply potential. The digital circuit includes a detecting circuit detecting a first delay caused by a first circuit connected to the first power supply potential, and a second circuit generating a control signal to control the analog circuit, the second circuit being connected to a second power supply potential whose potential variation is smaller than the first power supply potential. A second delay caused by the second circuit is controlled in correlation to the first delay.
    Type: Application
    Filed: November 29, 2010
    Publication date: June 2, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiromasa NODA
  • Patent number: 7940583
    Abstract: There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: May 10, 2011
    Assignee: Elpida Memory, Inc.
    Inventors: Yoshiro Riho, Jun Suzuki, Yasuhiro Matsumoto, Shuichi Kubouchi, Hiromasa Noda, Yasuji Koshikawa
  • Publication number: 20110026290
    Abstract: A semiconductor device includes a plurality of memory mats arranged in an X direction and a mat selecting circuit that activates a part of the memory mats based on a row address and maintains the rest of the memory mats inactivated. The memory mats are divided into a plurality of memory mat groups each including the same number of memory mats arranged in the X direction. The mat selecting circuit activates at least one of the memory mats included in each of the memory mat groups, while maintaining the rest of memory mats inactivated. With this operation, a portion of discontinuity does not occur in the memory mats arranged in the X direction, and thus the necessity of arranging two sub-word driver areas in the portion of discontinuity is eliminated.
    Type: Application
    Filed: August 2, 2010
    Publication date: February 3, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiromasa NODA, Yasuji KOSHIKAWA
  • Publication number: 20100142246
    Abstract: A semiconductor memory device comprises a plurality of memory cell mats, a plurality of sub-word driver regions and a plurality of sense amplifier regions, a plurality of intersection regions, a sub-amplifier, and a start signal (a control signal) supply circuit (a sub-amplifier control circuit). A plurality of sub-word driver regions and a plurality of sense amplifier regions are disposed adjacent to the plurality of memory cell mats. A plurality of intersection regions are intersection regions between the plurality of sub-word driver regions and the plurality of sense amplifier regions. The sub-amplifier is disposed in a first intersection region among the plurality of intersection regions. The start signal supply circuit is disposed in a second intersection region among the plurality of intersection regions, and supplies a start signal (a control signal) of the sub-amplifier to the sub-amplifier based on a sub-amplifier timing signal supplied from the extending direction of the sub-word driver region.
    Type: Application
    Filed: October 26, 2009
    Publication date: June 10, 2010
    Inventors: Tetsuaki OKAHIRO, Hiromasa Noda, Jun Suzuki
  • Publication number: 20100128548
    Abstract: A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
    Type: Application
    Filed: January 14, 2009
    Publication date: May 27, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Tetsuaki Okahiro, Hiromasa Noda, Katsunobu Noguchi
  • Publication number: 20100110817
    Abstract: A semiconductor device comprising a word line wired on a memory bank, a memory cell storing data provided in correspondence with the word line and a sense amplifier provided in correspondence with the word line, refreshing the memory cell corresponding to the word line selected by a row address that has been generated, including refresh counter 2 that generates a counter address corresponding to the row address and sequentially counts up the counter address, controller 1 that determines and outputs, upon receiving a refresh command instructing that a refresh operation be performed, first line number information and second line number information determining a number of word lines to be started based on the counter address and word line selector 3 that determines the row address according to the first line number information and the second line number information, and the counter address.
    Type: Application
    Filed: October 15, 2009
    Publication date: May 6, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiromasa Noda, Atsushi Fujikawa
  • Publication number: 20100109641
    Abstract: In a semiconductor device manufactured in a semiconductor chip, an internal circuit generates first and second internal circuit control signals which are produced as a delay time measurement start signal and a delay time measurement stop signal, respectively, which are sent to a delay time measurement circuit. The delay time measurement circuit measures a delay time between the start and the stop signals and outputs the delay time.
    Type: Application
    Filed: October 27, 2009
    Publication date: May 6, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiromasa Noda, Kenji Yoshida
  • Publication number: 20100066406
    Abstract: The semiconductor device may include, but is not limited to, a first switching circuit, a second switching circuit, and a control circuit. The first switching circuit switches between first and second states. The second switching circuit switches between the first and second states. The second switching circuit reduces a first power impedance across the first switching circuit. The control circuit is coupled to the first and second switching circuits. The control circuit keeps the first switching circuit in the first state. The control circuit switches the second switching circuit from the second state to the first state.
    Type: Application
    Filed: September 9, 2009
    Publication date: March 18, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiromasa Noda
  • Publication number: 20100034004
    Abstract: There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell; a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat.
    Type: Application
    Filed: August 7, 2009
    Publication date: February 11, 2010
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Tetsuaki OKAHIRO, Hiromasa NODA
  • Publication number: 20090268542
    Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.
    Type: Application
    Filed: July 9, 2009
    Publication date: October 29, 2009
    Applicant: Elpida Memory, Inc.
    Inventor: Hiromasa NODA
  • Patent number: 7586807
    Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: September 8, 2009
    Assignee: Elpida Memory, Inc.
    Inventor: Hiromasa Noda
  • Publication number: 20090201753
    Abstract: There are provided are a plurality of memory mats, a sub-word driver that accesses a normal memory cell irrespective of whether a row address to which access is requested is a defective address, a sub-word driver that accesses a redundant memory cell belonging to a memory mat different from the normal memory cell indicated by the row address, when the row address is a defective address. According to the present invention, the normal memory cell and a redundant memory cell belong to memory mats different to each other, and thus the normal memory cell can be accessed concurrently with determining operation of the repair determining circuit.
    Type: Application
    Filed: February 6, 2009
    Publication date: August 13, 2009
    Inventors: Yoshiro Riho, Jun Suzuki, Yasuhiro Matsumoto, Shuichi Kubouchi, Hiromasa Noda, Yasuji Koshikawa
  • Patent number: 7541839
    Abstract: A semiconductor device including an AND-NOR composite gate of which AND unit is supplied with input signals IN and VDD and NOR unit is supplied with an inverted signal EB of an enable signal E, and an AND-NOR composite gate of which AND unit is supplied with an input signal INB and an enable signal E and NOR unit is supplied with VSS. These gates are inserted into a path to which the input signals IN and INB are supplied. Thereby, a symmetric property of a complimentary signal can be retained. Further, outputs of the AND-NOR composite gates are fixed irrespective of a logical level of the enable signal E. Thus, a sub-threshold current also is inhibited.
    Type: Grant
    Filed: July 23, 2007
    Date of Patent: June 2, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Junichi Hayashi, Hiromasa Noda
  • Patent number: 7532036
    Abstract: A semiconductor device includes main power supply wirings VDD and VSS, an pseudo power supply wiring VDT, inverters connected between the pseudo power supply wiring VDT and the main power supply wiring VSS, and inverters connected between the main power supply wiring VDD and the main power supply wiring VSS. Between the main power supply wiring VDD and the pseudo power supply wiring VDT, an N-channel MOS transistor and a P-channel MOS transistor that are rendered a conductive state at the time of active are connected in parallel. According to the present invention, the transistors different in conductivity type are used in parallel, and thus, it becomes possible to reduce power consumption at the time of standby while suppressing a decrease in switching speed from a standby state to an active state.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: May 12, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Atsushi Fujikawa, Hiromasa Noda
  • Publication number: 20090059702
    Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
    Type: Application
    Filed: October 8, 2008
    Publication date: March 5, 2009
    Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
  • Patent number: 7450446
    Abstract: Disclosed is a semiconductor memory device configured to delay an input signal in accordance with a clock signal having a clock period. The semiconductor memory device comprises a reference signal generator and a delay circuit. The reference signal generator configured to generate a reference signal in accordance with the clock signal. The reference signal indicates a reference delay time representing the clock period. The delay circuit configured to delay input signal for a delay time to generate a delayed signal in accordance with the reference signal. The delay time is obtainable by multiplying the reference delay time by a positive integer.
    Type: Grant
    Filed: November 14, 2006
    Date of Patent: November 11, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Hiromasa Noda, Hiroki Fujisawa