Patents by Inventor Hiromasa Noda

Hiromasa Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7447091
    Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: November 4, 2008
    Assignees: Hitachi, Ltd., Elpida Memory, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
  • Publication number: 20080169840
    Abstract: A semiconductor device including an AND-NOR composite gate of which AND unit is supplied with input signals IN and VDD and NOR unit is supplied with an inverted signal EB of an enable signal E, and an AND-NOR composite gate of which AND unit is supplied with an input signal INB and an enable signal E and NOR unit is supplied with VSS. These gates are inserted into a path to which the input signals IN and INB are supplied. Thereby, a symmetric property of a complimentary signal can be retained. Further, outputs of the AND-NOR composite gates are fixed irrespective of a logical level of the enable signal E. Thus, a sub-threshold current also is inhibited.
    Type: Application
    Filed: July 23, 2007
    Publication date: July 17, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Junichi Hayashi, Hiromasa Noda
  • Publication number: 20080067551
    Abstract: Inverters are connected between a pseudo power supply wiring and a main power supply wiring, while inverters are connected between a main power supply wiring VDD and a pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Connected to the sources of transistors are switching areas for switching to the main power supply wiring or the pseudo power supply wiring. Even if improper connections are found or logical changes are required, the connection destination of the source is switched easily.
    Type: Application
    Filed: September 10, 2007
    Publication date: March 20, 2008
    Inventors: Yoshiro Riho, Ken Ota, Hiromasa Noda, Shinichi Miyatake
  • Publication number: 20080061833
    Abstract: A semiconductor device includes main power supply wirings VDD and VSS, an pseudo power supply wiring VDT, inverters connected between the pseudo power supply wiring VDT and the main power supply wiring VSS, and inverters connected between the main power supply wiring VDD and the main power supply wiring VSS. Between the main power supply wiring VDD and the pseudo power supply wiring VDT, an N-channel MOS transistor and a P-channel MOS transistor that are rendered a conductive state at the time of active are connected in parallel. According to the present invention, the transistors different in conductivity type are used in parallel, and thus, it becomes possible to reduce power consumption at the time of standby while suppressing a decrease in switching speed from a standby state to an active state.
    Type: Application
    Filed: August 23, 2007
    Publication date: March 13, 2008
    Inventors: Atsushi Fujikawa, Hiromasa Noda
  • Publication number: 20080019207
    Abstract: A semiconductor memory device includes a row control circuit block and a column control circuit block each performing an access control over a memory cell array, a data I/O circuit block transmitting and receiving data to and from the memory cell array, and a control circuit changing at least a part of the row control circuit block, the column control circuit block, and the data I/O circuit block from a standby state into an active state in response to a setting of a predetermined mode signal to a mode register. According to the present invention, even if it is necessary to turn predetermined circuit blocks into the active state by an operation other than a read or write operation, there is no need to always set these circuit blocks into the active state.
    Type: Application
    Filed: July 9, 2007
    Publication date: January 24, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Hiromasa Noda
  • Publication number: 20070147152
    Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
    Type: Application
    Filed: February 15, 2007
    Publication date: June 28, 2007
    Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
  • Publication number: 20070121394
    Abstract: Disclosed is a semiconductor memory device configured to delay an input signal in accordance with a clock signal having a clock period. The semiconductor memory device comprises a reference signal generator and a delay circuit. The reference signal generator configured to generate a reference signal in accordance with the clock signal. The reference signal indicates a reference delay time representing the clock period. The delay circuit configured to delay input signal for a delay time to generate a delayed signal in accordance with the reference signal. The delay time is obtainable by multiplying the reference delay time by a positive integer.
    Type: Application
    Filed: November 14, 2006
    Publication date: May 31, 2007
    Inventors: Hiromasa Noda, Hiroki Fujisawa
  • Patent number: 7200061
    Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: April 3, 2007
    Assignees: Hitachi, Ltd., Elpida Memory, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Tomonori Sekiguchi, Shinichi Miyatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
  • Patent number: 7184353
    Abstract: A semiconductor device capable of exchanging fuse data between registers is provided. Fuse circuits 20 to 24 are respectively connected to register circuits 10 to 14, and output fuse data that is stored in the built-in fuses to the respective register circuits 10 to 14. Register circuits 15 to 19 hold fuse data that is transferred from register circuits 10 to 14, respectively. A logic circuit 30 is connected to the output of the register circuits 15 to 19, and using the data held by the registers 15 to 19, calculated information such as whether or not an externally input address matches a salvage address for salvaging defective bits. Register circuits 10 and 11, 11 and 12, . . . , 17 and 18, 18 and 19 are connected to each other, and fuse data is transferred between adjacent register circuits. When doing this, pairs of adjacent register circuits operate such that data transfer is performed according to self-timing handshake logic.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: February 27, 2007
    Assignee: Elpida Memory, Inc.
    Inventor: Hiromasa Noda
  • Publication number: 20060114732
    Abstract: A semiconductor device capable of exchanging fuse data between registers is provided. Fuse circuits 20 to 24 are respectively connected to register circuits 10 to 14, and output fuse data that is stored in the built-in fuses to the respective register circuits 10 to 14. Register circuits 15 to 19 hold fuse data that is transferred from register circuits 10 to 14, respectively. A logic circuit 30 is connected to the output of the register circuits 15 to 19, and using the data held by the registers 15 to 19, calculated information such as whether or not an externally input address matches a salvage address for salvaging defective bits. Register circuits 10 and 11, 11 and 12, . . . , 17 and 18, 18 and 19 are connected to each other, and fuse data is transferred between adjacent register circuits. When doing this, pairs of adjacent register circuits operate such that data transfer is performed according to self-timing handshake logic.
    Type: Application
    Filed: November 28, 2005
    Publication date: June 1, 2006
    Applicant: Elpida Memory, Inc.
    Inventor: Hiromasa Noda
  • Publication number: 20060034133
    Abstract: A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
    Type: Application
    Filed: November 8, 2002
    Publication date: February 16, 2006
    Applicants: HITACHI, LTD., ELPIDA MEMORY, INC, HITACHI ULSI SYSTEM CO., LTD.
    Inventors: Tomonori Sekiguchi, Shinichi Myatake, Takeshi Sakata, Riichiro Takemura, Hiromasa Noda, Kazuhiko Kajigaya
  • Patent number: 6925017
    Abstract: A column select line YS1 can be enabled at the same time as the enabling of a word line. Write data is written from an I/O gate into a selected data line. An adjacent unselected sense amplifier reads data from memory cells. A source node of a cross-coupled sense amplifier connected to each data line pair is divided for each column select line, thereby to prevent a write-selected cross-coupled amplifier from driving the source node. In the write operation, data can be written at a high speed. On the other hand, it becomes possible to prevent a write-sense amplifier from driving the source node. Therefore, adjacent sense amplifiers can achieve stable read operation without being affected from the write-sense amplifier.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: August 2, 2005
    Assignees: Hitachi, Ltd., Elpida Memory, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Riichiro Takemura, Tomonori Sekiguchi, Takeshi Sakata, Shinichi Miyatake, Hiromasa Noda, Kazuhiko Kajigaya
  • Patent number: 6882557
    Abstract: The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased. The switches are connected to one-side ends of the bit lines provided at the odd-numbered positions, and are connected to the other-side ends of the bit lines provided at the even-numbered positions. A pair of odd-numbered or even-numbered bit lines are connected to the terminals of each sense amplifier, respectively. The memory cells are arranged at predetermined intersection points of the word lies and the bit lines, the number of the predetermined intersection points being equal to half of all the intersection points thereof, in such a manner that when one word line is selected, the memory cells connected to the selected word-line can be electrically connected in such a manner that one memory cell is electrically connected to each terminal of the unit circuits.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: April 19, 2005
    Inventors: Kazuhiko Kajigaya, Hiromasa Noda, Shinichi Miyatake, Riichiro Takemura, Tomonori Sekiguchi, Takeshi Sakata
  • Publication number: 20040184304
    Abstract: The contact resistance of each switch is reduced, and the on-resistances of all of the switches are set to be uniform, while the area required for arrangement of bit line selection switches is not increased.
    Type: Application
    Filed: September 5, 2003
    Publication date: September 23, 2004
    Inventors: Kazuhiko Kajigaya, Hiromasa Noda, Shinichi Miyatake, Riichiro Takemura, Tomonori Sekiguchi, Takeshi Sakata
  • Publication number: 20040124440
    Abstract: A column select line YS1 can be enabled at the same time as the enabling of a word line. Write data is written from an I/O gate into a selected data line. An adjacent unselected sense amplifier reads data from memory cells. A source node of a cross-coupled sense amplifier connected to each data line pair is divided for each column select line, thereby to prevent a write-selected cross-coupled amplifier from driving the source node. In the write operation, data can be written at a high speed. On the other hand, it becomes possible to prevent a write-sense amplifier from driving the source node. Therefore, adjacent sense amplifiers can achieve stable read operation without being affected from the write-sense amplifier.
    Type: Application
    Filed: November 6, 2003
    Publication date: July 1, 2004
    Inventors: Riichiro Takemura, Tomonori Sekiguchi, Takeshi Sakata, Shinichi Miyatake, Hiromasa Noda, Kazuhiko Kajigaya
  • Patent number: 6535435
    Abstract: A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential amplifier significantly increase. A push-pull conversion circuit is coupled to the differential amplifier and has a double end configuration to provide a sufficiently high level to drive a p-channel output buffer. This arrangement allows a stable operation at a sufficiently low power supply voltage even if the threshold voltages of the MOSFETs forming the differential amplifier are high. It also allows quick activation when the power is turned on and provides high stability.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: March 18, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hitoshi Tanaka, Masakazu Aoki, Shinichiro Kimura, Hiromasa Noda, Tomonori Sekiguchi
  • Patent number: 6498762
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: December 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata
  • Patent number: 6496403
    Abstract: Disclosed a semiconductor memory device in which an access to a memory cell is designated according to a command, and a common data terminal is used as an input terminal to which a write signal to the memory cell is input and an output terminal from which a read signal from the memory cell is output. The semiconductor memory device includes: a first input circuit having input capacitance corresponding to the input terminal to which the command is input; and a second input circuit having input capacitance corresponding to the data terminal. A mask signal for checking the write signal input from the data terminal is input by either the first or second input circuit by a bonding option technique.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: December 17, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Sadayuki Okuma, Hiroshi Ichikawa, Hiroki Miyashita, Yasushi Takahashi
  • Patent number: 6473358
    Abstract: A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: October 29, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Youji Idei, Osamu Nagashima, Tetsuo Ado
  • Patent number: 6473354
    Abstract: A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: October 29, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiromasa Noda, Masakazu Aoki, Youji Idei, Kazuhiko Kajigaya, Osamu Nagashima, Kiyoo Itoh, Masashi Horiguchi, Takeshi Sakata