Patents by Inventor Hiromasa YOSHIMORI
Hiromasa YOSHIMORI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11756898Abstract: A semiconductor memory device includes: two memory blocks; a first structure disposed between the two memory blocks; and a second structure separated from the two memory blocks, or a plurality of second structures. The two memory blocks include a plurality of first conductive layers and a plurality of first insulating layers alternately arranged. The first structure has one end, and the one end is closer to the substrate than the plurality of first conductive layers are. The second structure has one end, and the one end is closer to the substrate than at least apart of the first conductive layers among the plurality of first conductive layers is. Another end of the first structure and another end of the second structure are farther from the substrate than the plurality of first conductive layers are. The second structure is separated from the first structure.Type: GrantFiled: December 14, 2020Date of Patent: September 12, 2023Assignee: KIOXIA CORPORATIONInventors: Hideki Itai, Mitsuhiro Noguchi, Hiromasa Yoshimori, Hideyuki Tabata, Yasushi Nakajima
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Publication number: 20220005767Abstract: A semiconductor memory device includes: two memory blocks; a first structure disposed between the two memory blocks; and a second structure separated from the two memory blocks, or a plurality of second structures. The two memory blocks include a plurality of first conductive layers and a plurality of first insulating layers alternately arranged. The first structure has one end, and the one end is closer to the substrate than the plurality of first conductive layers are. The second structure has one end, and the one end is closer to the substrate than at least apart of the first conductive layers among the plurality of first conductive layers is. Another end of the first structure and another end of the second structure are farther from the substrate than the plurality of first conductive layers are. The second structure is separated from the first structure.Type: ApplicationFiled: December 14, 2020Publication date: January 6, 2022Applicant: KIOXIA CORPORATIONInventors: Hideki ITAI, Mitsuhiro NOGUCHI, Hiromasa YOSHIMORI, Hideyuki TABATA, Yasushi NAKAJIMA
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Patent number: 10833006Abstract: A semiconductor device includes a substrate, a first electrode provided apart from the surface of the substrate in a first direction intersecting the surface of the substrate, a second electrode extending completely through the substrate in the first direction and connected to the first electrode at one end in the first direction, a first structure covering a side surface of the second electrode, and an insulating film provided between the second electrode and the first structure. The second electrode includes first atoms, and the first structure includes second atoms. A diffusion coefficient of the second atoms in the insulating film is smaller than a diffusion coefficient of the first atoms in the insulating film.Type: GrantFiled: February 20, 2019Date of Patent: November 10, 2020Assignee: Toshiba Memory CorporationInventors: Hiromasa Yoshimori, Masayuki Ako
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Publication number: 20200075481Abstract: A semiconductor device includes a substrate, a first electrode provided apart from the surface of the substrate in a first direction intersecting the surface of the substrate, a second electrode extending completely through the substrate in the first direction and connected to the first electrode at one end in the first direction, a first structure covering a side surface of the second electrode, and an insulating film provided between the second electrode and the first structure. The second electrode includes first atoms, and the first structure includes second atoms. A diffusion coefficient of the second atoms in the insulating film is smaller than a diffusion coefficient of the first atoms in the insulating film.Type: ApplicationFiled: February 20, 2019Publication date: March 5, 2020Inventors: Hiromasa YOSHIMORI, Masayuki AKO
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Patent number: 10056315Abstract: A semiconductor device of an embodiment includes a semiconductor layer, a first conductor, a first conductive layer, a first insulating layer, a second conductive layer, and a plurality of second conductors. The semiconductor layer has a first region and a second region. The first conductor is provided in the semiconductor layer. The first conductive layer is electrically connected to the first conductor. The first insulating layer is provided in the semiconductor layer with at least part of the first insulating layer being provided between the first conductive layer and the semiconductor layer. A distance from the first insulating layer to the first region is smaller than a distance to the second region. A first distance to the first region from a plane that includes a first interface between the first insulating layer and the first conductive layer is larger than a second distance from the plane to the second region.Type: GrantFiled: March 6, 2017Date of Patent: August 21, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masayuki Akou, Hiromasa Yoshimori, Yoshihiro Sobue
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Publication number: 20180068928Abstract: A semiconductor device of an embodiment includes a semiconductor layer, a first conductor, a first conductive layer, a first insulating layer, a second conductive layer, and a plurality of second conductors. The semiconductor layer has a first region and a second region. The first conductor is provided in the semiconductor layer. The first conductive layer is electrically connected to the first conductor. The first insulating layer is provided in the semiconductor layer with at least part of the first insulating layer being provided between the first conductive layer and the semiconductor layer. A distance from the first insulating layer to the first region is smaller than a distance to the second region. A first distance to the first region from a plane that includes a first interface between the first insulating layer and the first conductive layer is larger than a second distance from the plane to the second region.Type: ApplicationFiled: March 6, 2017Publication date: March 8, 2018Applicant: Toshiba Memory CorporationInventors: Masayuki AKOU, Hiromasa YOSHIMORI, Yoshihiro SOBUE
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Patent number: 9831259Abstract: Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.Type: GrantFiled: September 27, 2016Date of Patent: November 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hiromasa Yoshimori, Hirofumi Tokita
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Publication number: 20170077114Abstract: A semiconductor memory device includes a first word line that is provided above a semiconductor substrate, a second word line that is provided above the first word line, a plurality of semiconductor pillars that are provided on the semiconductor substrate, and pass through the first and second word lines, and first and second plugs that are provided so that the plurality of semiconductor pillars are interposed therebetween. The semiconductor substrate includes an insulating region that is provided deeper than a bottom of the first plug relative to a surface of the semiconductor substrate, between the first plug and one of the semiconductor pillars.Type: ApplicationFiled: August 10, 2016Publication date: March 16, 2017Inventors: Hiromasa YOSHIMORI, Hiroshi SHINOHARA
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Publication number: 20170018556Abstract: Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.Type: ApplicationFiled: September 27, 2016Publication date: January 19, 2017Inventors: Hiromasa YOSHIMORI, Hirofumi TOKITA
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Patent number: 9460929Abstract: Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.Type: GrantFiled: February 28, 2015Date of Patent: October 4, 2016Assignee: Renesas Electronics CorporationInventors: Hiromasa Yoshimori, Hirofumi Tokita
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Patent number: 9184053Abstract: An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.Type: GrantFiled: January 7, 2013Date of Patent: November 10, 2015Assignee: Renesas Electronics CorporationInventors: Hirofumi Shinohara, Hiromasa Yoshimori, Toshiaki Iwamatsu, Hidekazu Oda
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Publication number: 20150249145Abstract: Provided is a semiconductor device having improved performance. Over a semiconductor substrate, a dummy control gate electrode is formed via a first insulating film. Over the semiconductor substrate, a memory gate electrode for a memory cell is formed via a second insulating film having an internal charge storage portion so as to be adjacent to the dummy control gate electrode. At this time, the height of the memory gate electrode is adjusted to be lower than the height of the dummy control gate electrode. Then, a third insulating film is formed so as to cover the dummy control gate electrode and the memory gate electrode. Then, the third insulating film is polished to expose the dummy control gate electrode. At this time, the memory gate electrode is not exposed. Then, the dummy control gate electrode is removed and replaced with a metal gate electrode.Type: ApplicationFiled: February 28, 2015Publication date: September 3, 2015Inventors: Hiromasa YOSHIMORI, Hirofumi TOKITA
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Patent number: 9054102Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.Type: GrantFiled: July 11, 2014Date of Patent: June 9, 2015Assignee: Renesas Electronics CorporationInventors: Hiromasa Yoshimori, Hirofumi Shinohara, Toshiaki Iwamatsu
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Publication number: 20140319618Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.Type: ApplicationFiled: July 11, 2014Publication date: October 30, 2014Inventors: Hiromasa YOSHIMORI, Hirofumi Shinohara, Toshiaki Iwamatsu
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Patent number: 8809959Abstract: The performances of a semiconductor device are improved. The device includes a first MISFET in which hafnium is added to the gate electrode side of a first gate insulation film including silicon oxynitride, and a second MISFET in which hafnium is added to the gate electrode side of a second gate insulation film including silicon oxynitride. The hafnium concentration in the second gate insulation film of the second MISFET is set smaller than the hafnium concentration in the first gate insulation film of the first MISFET; and the nitrogen concentration in the second gate insulation film of the second MISFET is set smaller than the nitrogen concentration in the first gate insulation film of the first MISFET. As a result, the threshold voltage of the second MISFET is adjusted to be smaller than the threshold voltage of the first MISFET.Type: GrantFiled: December 4, 2012Date of Patent: August 19, 2014Assignee: Renesas Electronics CorporationInventors: Hiromasa Yoshimori, Hirofumi Shinohara, Toshiaki Iwamatsu
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Publication number: 20140042552Abstract: Provided is a semiconductor device having an insulating gate field effect transistor equipped with a metal oxide film in a portion, on the side of a source region, between a gate insulating film and a gate electrode. The metal oxide film is provided above a p+ type semiconductor region for punch-through stopper so as to cover the entire region thereof. Such a metal oxide film contributes to a decrease in the impurity concentration of the p+ type semiconductor region, making it possible to reduce variations in the threshold voltage of the transistor. On the side of a drain region, the gate insulating film is formed as a single film without stacking the metal oxide film thereon. As a result, the resulting transistor can escape deterioration in reliability which will otherwise occur due to hot carriers on the side of the end of the drain region.Type: ApplicationFiled: August 4, 2013Publication date: February 13, 2014Applicant: Renesas Electronics CorporationInventors: Hiromasa Yoshimori, Toshiaki Iwamatsu
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Publication number: 20120007151Abstract: A high breakdown voltage circuit containing a high breakdown voltage MOSFET in LSI, unlike a quintessential internal circuit, has an operating voltage fixed in a high state due to the relation with the outside and, therefore, miniaturization by the voltage lowering can not be applied, differing from ordinary cases. Consequently, the voltage lowering of an internal circuit part results in a furthermore enlargement of occupying area in the chip. The present inventors evaluated various measures for the problem, and made it clear that such problems as compatibility with the CMOSFET circuit configuration and device configuration, etc. constitute obstacles.Type: ApplicationFiled: June 22, 2011Publication date: January 12, 2012Inventors: Hiromasa YOSHIMORI, Toshiaki Iwamatsu