Patents by Inventor Hiromi Hoshino

Hiromi Hoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11938980
    Abstract: A RIO device mounted to a train includes an output unit that outputs a signal to a relay mounted to the train, and a controller that controls whether or not to cause the output unit to output the signal. The output unit includes a readback circuit that detects whether or not the signal is outputted from the output unit. The controller makes a signal stop request and a signal output request to the output unit before operation of the train starts, acquires a detection result of the readback circuit while each of the signal stop request and the signal output request is performed, and detects abnormality of the output unit using the detection result.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: March 26, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Ken Shibata, Tetsuo Komura, Hiromi Goda, Hiroshi Jota, Kentaro Hoshino
  • Publication number: 20240069723
    Abstract: A memory system connectable to a host includes a nonvolatile memory and a controller. The nonvolatile memory includes physical blocks. The controller is configured to assign each of a plurality of block groups, each block group including a predetermined number or more of the physical blocks, to one of categories. The controller assigns block groups having a total capacity equal to a fraction of the overprovisioning capacity that is equal to a first threshold value, to the first category, and block groups having a total capacity equal to a remaining part of the overprovisioning capacity to the third category. When an overprovisioning ratio falls below a second threshold value, the controller reassigns one or more block groups in the third category to the first category.
    Type: Application
    Filed: February 27, 2023
    Publication date: February 29, 2024
    Inventors: Hiromi HOSHINO, Yoko MASUO
  • Patent number: 9179117
    Abstract: According to one embodiment, an image processing apparatus includes, an error detector configured to make an error check of the stream received, a player configured to reproduce the stream, a memory configured to store a plurality of pieces of displaying data indicating formats of the streams that can be processed by the image processing apparatus, a transmitter configured to transmit the pieces of displaying data stored in the memory to the external device in response to a request from the external device, and a rewriting module configured to delete one piece of displaying data stored in the memory when an error is detected by the error detector.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: November 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiromi Hoshino, Yusuke Ikeda
  • Publication number: 20140240465
    Abstract: [Object] To preferably set a focus distance and a convergence distance. [Solving Means] A three-dimensional image pickup apparatus 100 is provided with a left lens optical system 121L and a right lens optical system 121R including a pair of right and left image pickup lenses disposed at a predetermined inter axial distance. Further, a focus ring that adjusts the focus of the left lens optical system 121L and the right lens optical system 121R and a control circuit that adjusts a convergence distance from a convergence point at which optical axes of the pair of right and left image pickup lenses are intersected to the image pickup lenses. The control circuit adds the offset distance to the focus distance and adjusts the convergence distance with the offset distance set as a distance from a focus point to a convergence point to be set.
    Type: Application
    Filed: March 15, 2012
    Publication date: August 28, 2014
    Applicant: Sony Corporation
    Inventors: Masamiki Kawase, Hiromi Hoshino
  • Publication number: 20140003794
    Abstract: According to one embodiment, an image processing apparatus includes, an error detector configured to make an error check of the stream received, a player configured to reproduce the stream, a memory configured to store a plurality of pieces of displaying data indicating formats of the streams that can be processed by the image processing apparatus, a transmitter configured to transmit the pieces of displaying data stored in the memory to the external device in response to a request from the external device, and a rewriting module configured to delete one piece of displaying data stored in the memory when an error is detected by the error detector.
    Type: Application
    Filed: August 22, 2013
    Publication date: January 2, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiromi HOSHINO, Yusuke IKEDA
  • Patent number: 8553198
    Abstract: In view of realizing a lithographic process which makes it possible to estimate and correct flare with an extremely high accuracy, and causes only an extremely small dimensional variation in width, over the entire portion not only of a single shot region, but also of a single chip region, a mask pattern correction device of the present invention has a numerical aperture calculation unit calculating, for every single shot region, flare energy for a mask pattern corresponding to a transferred pattern, based on an exposure layout of a plurality of shot regions, or more specifically, while considering flare from a plurality of shot regions located around every single shot region.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: October 8, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Teruyoshi Yao, Satoru Asai, Morimi Osawa, Hiromi Hoshino, Kouzou Ogino, Kazumasa Morishita
  • Patent number: 8429573
    Abstract: A method includes: generating electron beam exposure data, used for electron beam exposure, from design data of a semiconductor device; extracting differential information indicating a difference in shape between an electron beam exposure pattern formed on a substrate through electron beam exposure on the basis of the electron beam exposure data and a photoexposure pattern formed on the substrate through photoexposure on the basis of the design data of the semiconductor device; determining whether the size of the difference in shape between the electron beam exposure pattern and the photoexposure pattern falls within a predetermined reference value; acquiring shape changed exposure data by changing the shape of the pattern of the electron beam exposure data in accordance with the differential information and updating the electron beam exposure data; and repeating the differential extraction, the determination and the updating when the size of the difference falls outside the predetermined reference value.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: April 23, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kozo Ogino, Hiromi Hoshino
  • Publication number: 20120236279
    Abstract: In view of realizing a lithographic process which makes it possible to estimate and correct flare with an extremely high accuracy, and causes only an extremely small dimensional variation in width, over the entire portion not only of a single shot region, but also of a single chip region, a mask pattern correction device of the present invention has a numerical aperture calculation unit calculating, for every single shot region, flare energy for a mask pattern corresponding to a transferred pattern, based on an exposure layout of a plurality of shot regions, or more specifically, while considering flare from a plurality of shot regions located around every single shot region.
    Type: Application
    Filed: June 4, 2012
    Publication date: September 20, 2012
    Applicant: FUJITSU SEMICONDUCTOR LTD
    Inventors: Teruyoshi YAO, Satoru Asai, Morimi Osawa, Hiromi Hoshino, Kouzou Ogino, Kazumasa Morishita
  • Patent number: 8227153
    Abstract: In view of realizing a lithographic process which makes it possible to estimate and correct flare with an extremely high accuracy, and causes only an extremely small dimensional variation in width, over the entire portion not only of a single shot region, but also of a single chip region, a mask pattern correction device of the present invention has a numerical aperture calculation unit calculating, for every single shot region, flare energy for a mask pattern corresponding to a transferred pattern, based on an exposure layout of a plurality of shot regions, or more specifically, while considering flare from a plurality of shot regions located around every single shot region.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: July 24, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Teruyoshi Yao, Satoru Asai, Morimi Osawa, Hiromi Hoshino, Kouzou Ogino, Kazumasa Morishita
  • Patent number: 8141009
    Abstract: A method for preparing data for exposure includes forming a first plurality of rectangular patterns from a reticle preparing rule; lining an object pattern for performing reticle exposure with the first rectangular patterns, and extracting a second plurality of rectangular patterns, disposed in an N×N matrix, from the first plurality of rectangular patterns in the object pattern; and performing a violation detecting treatment and a correcting treatment of the pattern width and the pattern distance of the reticle exposure pattern on the basis of the distance between the second plurality of rectangular patterns.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: March 20, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masaaki Miyajima, Hiromi Hoshino, Hiroshi Takita, Kozo Ogino
  • Patent number: 8136057
    Abstract: A semiconductor manufacturing method comprising, a data generating process including, acquiring a simulation light pattern that simulates a shape of a light exposure pattern formed on a substrate on the basis of design data of a semiconductor device, acquiring a simulation electron beam exposure pattern that simulates a shape of an electron beam exposure pattern formed by an electron beam exposure on the substrate on the basis of the design data, extracting difference information representing a shape difference portion between the simulation light pattern and the simulation electron beam exposure pattern, acquiring changed design data for modifying shape by changing the design data in accordance with the difference information, conducting the electron beam exposure on the substrate by use of the changed design data for modifying the shape.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: March 13, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiromi Hoshino
  • Publication number: 20120030322
    Abstract: According to one embodiment, a data transceiver accepts a new application file, and a setting information processor transfers and copies setting information described in a setting information area of an existent application file, to a corresponding setting information area of the new application file.
    Type: Application
    Filed: April 14, 2011
    Publication date: February 2, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideo KATAOKA, Hiromi HOSHINO
  • Publication number: 20110320987
    Abstract: A semiconductor manufacturing method comprising, a data generating process including, acquiring a simulation light pattern that simulates a shape of a light exposure pattern formed on a substrate on the basis of design data of a semiconductor device, acquiring a simulation electron beam exposure pattern that simulates a shape of an electron beam exposure pattern formed by an electron beam exposure on the substrate on the basis of the design data, extracting difference information representing a shape difference portion between the simulation light pattern and the simulation electron beam exposure pattern, acquiring changed design data for modifying shape by changing the design data in accordance with the difference information, conducting the electron beam exposure on the substrate by use of the changed design data for modifying the shape.
    Type: Application
    Filed: September 1, 2011
    Publication date: December 29, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Hiromi HOSHINO
  • Patent number: 8081864
    Abstract: An image of an object is picked up by an image processing unit (10) to acquire an image signal of variable frame rate. An audio signal is acquired by an audio processing unit (20) to generate an audio signal having the number of frames caused to be in conformity with the system frame rate to generate a recording signal of recording frame rate from the image signal of the variable frame rate and an audio signal having the number of frames caused to be in conformity with the system frame rate. In recording a recording signal of the recording frame rate onto or into a recording medium (35) by a recording/reproducing unit (30), discrimination information indicating image pick-up frame rate and system frame rate is recorded onto or into the recording medium (35), e.g., as MXF (Material Exchange Format) file along with the image signal of the variable frame rate and the audio signal having the number of frames caused to be in conformity with the system frame rate.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: December 20, 2011
    Assignee: Sony Corporation
    Inventor: Hiromi Hoshino
  • Patent number: 8032844
    Abstract: A semiconductor manufacturing method comprising, a data generating process including, acquiring a simulation light pattern that simulates a shape of a light exposure pattern formed on a substrate on the basis of design data of a semiconductor device, acquiring a simulation electron beam exposure pattern that simulates a shape of an electron beam exposure pattern formed by an electron beam exposure on the substrate on the basis of the design data, extracting difference information representing a shape difference portion between the simulation light pattern and the simulation electron beam exposure pattern, acquiring changed design data for modifying shape by changing the design data in accordance with the difference information, conducting the electron beam exposure on the substrate by use of the changed design data for modifying the shape.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiromi Hoshino
  • Patent number: 7968259
    Abstract: In a multi-project-chip semiconductor device, semiconductor elements fabricated on a wafer have a layout that corresponds to an exposure order of a pattern of the semiconductor elements and that is based on information indicating manufacture conditions and the number of shots and are arranged such that the semiconductor elements having the same manufacture condition are adjacent to each other in ascending or descending order of the number of shots.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiromi Hoshino, Takashi Maruyama
  • Patent number: 7861210
    Abstract: An exposure data generator for generating exposure data representing graphical information of a pattern to be exposed and a computer-readable recording medium are provided. The generator includes a storage device for storing pre-correction exposure data which include information on positions and sizes of patterns placed within an target region and a search device for classifying the patterns according to placement positions within the target region, searching for a pattern which is another pattern by using the classified patterns, and storing information on the patterns. The generator also includes a back-scattering intensity calculation device for calculating a back-scattering intensity from at an evaluation point on the pattern. The generator also includes a movement quantity calculation device for calculating a movement quantity of a side of a pattern.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: December 28, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kozo Ogino, Hiromi Hoshino
  • Publication number: 20100209834
    Abstract: In view of realizing a lithographic process which makes it possible to estimate and correct flare with an extremely high accuracy, and causes only an extremely small dimensional variation in width, over the entire portion not only of a single shot region, but also of a single chip region, a mask pattern correction device of the present invention has a numerical aperture calculation unit calculating, for every single shot region, flare energy for a mask pattern corresponding to a transferred pattern, based on an exposure layout of a plurality of shot regions, or more specifically, while considering flare from a plurality of shot regions located around every single shot region.
    Type: Application
    Filed: April 26, 2010
    Publication date: August 19, 2010
    Applicant: FUJITSU SEMICONDUCTOR LTD.
    Inventors: Teruyoshi YAO, Satoru ASAI, Morimi OSAWA, Hiromi HOSHINO, Kouzou OGINO, Kazumasa MORISHITA
  • Patent number: 7732107
    Abstract: In view of realizing a lithographic process which makes it possible to estimate and correct flare with an extremely high accuracy, and causes only an extremely small dimensional variation in width, over the entire portion not only of a single shot region, but also of a single chip region, a mask pattern correction device of the present invention has a numerical aperture calculation unit calculating, for every single shot region, flare energy for a mask pattern corresponding to a transferred pattern, based on an exposure layout of a plurality of shot regions, or more specifically, while considering flare from a plurality of shot regions located around every single shot region.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: June 8, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Teruyoshi Yao, Satoru Asai, Morimi Osawa, Hiromi Hoshino, Kouzou Ogino, Kazumasa Morishita
  • Patent number: 7623176
    Abstract: The present invention provides a meta-data display system capable of displaying meta data related to a shot video material along with the video material synchronously to the material. The meta-data display system includes an imaging apparatus for generating a video signal representing the video material. The meta-data display system also has a meta-data synthesis apparatus for extracting at least a part of meta data from the video signal including the meta data added for every frame and synthesizing the extracted part with the video signal. The meta-data display system also includes display apparatus each used for displaying a video signal including meta data synthesized therewith. In such a configuration, a part of meta data added to a video signal is extracted and converted into video data, which is then multiplexed in the video signal of every frame.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: November 24, 2009
    Assignee: Sony Corporation
    Inventors: Hiromi Hoshino, Fumio Nakajima