Patents by Inventor Hiromi Shigihara

Hiromi Shigihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8592984
    Abstract: To suppress peeling of an Au pad for external coupling provided in a rewiring containing Cu as a main component. On the surface of a rewiring including a two-layer film in which a first Ni film is laminated on the top of a Cu film, a pad to which a wire is coupled is formed. The pad includes a two-layer film in which an Au film is laminated on the top of a second Ni film and formed integrally so as to cover the top surface and the side surface of the rewiring. Due to this, the area of contact between the rewiring and the pad increases, and therefore, the pad becomes difficult to be peeled off from the rewiring.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: November 26, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromi Shigihara, Akira Yajima, Hisao Shigihara, Hiroshi Tsukamoto
  • Patent number: 8435868
    Abstract: With a general wafer level package process, in order to prevent corrosion of an aluminum type pad electrode in a scribe region in a plating process, the pad electrode is covered with a pad protective resin film at the same layer as an organic type protective film in a product region. However, this makes it impossible to perform the probe test on the pad electrode in the scribe region after rewiring formation. The present invention provides a method for manufacturing a semiconductor integrated circuit device of a wafer level package system. The organic type protective films in the chip regions and the scribe region are mutually combined to form an integral film pattern. In a pelletization step, the surface layer portion including the organic type protective film at the central part of the scribe region is first removed by laser grooving, to form a large-width groove. Then, a dicing processing of the central part in this groove results in separation into the chip regions.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: May 7, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hisao Shigihara, Hiromi Shigihara, Akira Yajima
  • Publication number: 20120235278
    Abstract: Adhesive strength between a rewiring and a solder bump is improved in a semiconductor integrated circuit device in which a bump electrode is connected to a land section of the rewiring. The land section 20A of the rewiring 20 is formed by a five-layer metal film (a barrier metal film 13, a seed film 14, a Cu film 15, a first Ni film 16, and a second Ni film 17) constituting the rewiring 20, the uppermost-layer second Ni film 17 has a larger area than that of the other metal films (the barrier metal film 13, the seed film 14, the Cu film 15, and the first Ni film 16). A solder bump 21 is connected to the surface of the second Ni film 17. At the end portion of the solder bump 21, a polyimide resin film 22 is formed directly under the second Ni film 17.
    Type: Application
    Filed: February 27, 2012
    Publication date: September 20, 2012
    Inventors: Hisao Shigihara, Hiromi Shigihara, Akira Yajima
  • Publication number: 20120032329
    Abstract: In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).
    Type: Application
    Filed: September 12, 2011
    Publication date: February 9, 2012
    Inventors: HIROMI SHIGIHARA, HIROSHI TSUKAMOTO, AKIRA YAJIMA
  • Publication number: 20110304049
    Abstract: To suppress peeling of an Au pad for external coupling provided in a rewiring containing Cu as a main component. On the surface of a rewiring including a two-layer film in which a first Ni film is laminated on the top of a Cu film, a pad to which a wire is coupled is formed. The pad includes a two-layer film in which an Au film is laminated on the top of a second Ni film and formed integrally so as to cover the top surface and the side surface of the rewiring. Due to this, the area of contact between the rewiring and the pad increases, and therefore, the pad becomes difficult to be peeled off from the rewiring.
    Type: Application
    Filed: June 14, 2011
    Publication date: December 15, 2011
    Inventors: Hiromi SHIGIHARA, Akira Yajima, Hisao Shigihara, Hiroshi Tsukamoto
  • Patent number: 8063489
    Abstract: In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.).
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromi Shigihara, Hiroshi Tsukamoto, Akira Yajima
  • Publication number: 20100181650
    Abstract: With a general wafer level package process, in order to prevent corrosion of an aluminum type pad electrode in a scribe region in a plating process, the pad electrode is covered with a pad protective resin film at the same layer as an organic type protective film in a product region. However, this makes it impossible to perform the probe test on the pad electrode in the scribe region after rewiring formation. The present invention provides a method for manufacturing a semiconductor integrated circuit device of a wafer level package system. The organic type protective films in the chip regions and the scribe region are mutually combined to form an integral film pattern. In a pelletization step, the surface layer portion including the organic type protective film at the central part of the scribe region is first removed by laser grooving, to form a large-width groove. Then, a dicing processing of the central part in this groove results in separation into the chip regions.
    Type: Application
    Filed: December 30, 2009
    Publication date: July 22, 2010
    Inventors: Hisao SHIGIHARA, Hiromi Shigihara, Akira Yajima
  • Publication number: 20100133688
    Abstract: In semiconductor integrated circuit devices for vehicle use or the like, in general, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding or the like using a gold wire and the like for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.).
    Type: Application
    Filed: December 1, 2009
    Publication date: June 3, 2010
    Inventors: Hiromi Shigihara, Hiroshi Tsukamoto, Akira Yajima
  • Publication number: 20090315179
    Abstract: A semiconductor device having projection electrodes with a narrow pad pitch, and a method of forming such semiconductor device, are provided. On a semiconductor wafer, a polyimide film, which does not cover each of a plurality of lands, is prepared between the respective lands which adjoin each other among the plurality of lands on the main surface of the semiconductor wafer. A soldering paste material is applied by a printing method, via a mask for printing, on each of a plurality of lands after polyimide film formation, and a solder bump is formed by performing heat curing of the soldering paste material after removing the mask for printing. The solder bump can be provided without generating an electric short circuit between bumps even in the case of a narrow pad pitch.
    Type: Application
    Filed: August 26, 2009
    Publication date: December 24, 2009
    Inventors: Hiromi SHIGIHARA, Hisao Shigihara, Akira Yajima
  • Publication number: 20060131365
    Abstract: Realization of the projection electrode formation with a narrow pad pitch is planned. In preparing a semiconductor wafer, by forming a polyimide film, which does not cover each of a plurality of lands, between the respective lands which adjoin each other among the plurality of lands on the main surface of the semiconductor wafer, applying a soldering paste material with the printing method via the mask for printing on each of a plurality of lands after polyimide film formation, and forming a solder bump by performing heat curing of the soldering paste material after removing the mask for printing, a solder bump can be formed without generating a electric short circuit between bumps even in the case of a narrow pad pitch.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 22, 2006
    Inventors: Hiromi Shigihara, Hisao Shigihara, Akira Yajima