Patents by Inventor Hiromichi Godo

Hiromichi Godo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9997638
    Abstract: An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 12, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Kengo Akimoto, Shunpei Yamazaki
  • Publication number: 20180090710
    Abstract: A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 29, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hiromichi Godo, Kaoru Tsuchiya
  • Patent number: 9887297
    Abstract: A semiconductor device includes a gate electrode having higher Gibbs free energy for oxidation than a gate insulating film. An oxide semiconductor layer having a fin shape is formed over an insulating surface, a gate insulating film is formed over the oxide semiconductor layer, a gate electrode including an oxide layer and facing top and side surfaces of the oxide semiconductor layer with the gate insulating film located therebetween is formed, and then by performing heat treatment, a gate electrode is reduced and oxygen is supplied to the oxide semiconductor layer through the gate insulating film.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Hiromichi Godo
  • Patent number: 9859443
    Abstract: Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film. The gate electrode partly overlaps a source electrode and a drain electrode. The source electrode and the drain electrode are in contact with at least a top surface of the oxide semiconductor. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate electrode, so that electrons injected from the source electrode or the drain electrode can be effectively removed, and most of the space between the source electrode and the drain electrode can be a depletion region; thus, off-state current can be reduced.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Yasuhiko Takemura
  • Publication number: 20170373193
    Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 28, 2017
    Inventors: Shunpei YAMAZAKI, Hiromichi GODO, Satoshi KOBAYASHI
  • Patent number: 9852108
    Abstract: Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 26, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo
  • Publication number: 20170309721
    Abstract: The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.
    Type: Application
    Filed: July 6, 2017
    Publication date: October 26, 2017
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Hiroshi FUJIKI, Hiromichi GODO, Yasumasa YAMANE
  • Patent number: 9799773
    Abstract: A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: October 24, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hiromichi Godo, Satoshi Kobayashi, Masashi Tsubuku
  • Patent number: 9780329
    Abstract: A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hiromichi Godo, Kaoru Tsuchiya
  • Patent number: 9761588
    Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes a wide-gap semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo
  • Publication number: 20170256650
    Abstract: An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.
    Type: Application
    Filed: May 18, 2017
    Publication date: September 7, 2017
    Inventors: Hiromichi GODO, Kengo AKIMOTO, Shunpei YAMAZAKI
  • Patent number: 9748401
    Abstract: Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: ?1 and ?2, ?1<?2 is satisfied, and ?2 is 300 seconds or less. In addition, a semiconductor device including the transistor is manufactured.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 29, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masashi Tsubuku, Takayuki Inoue, Suzunosuke Hiraishi, Erumu Kikuchi, Hiromichi Godo, Shuhei Yoshitomi, Koki Inoue, Akiharu Miyanaga, Shunpei Yamazaki
  • Publication number: 20170213833
    Abstract: To provide a semiconductor device with large storage capacity and low power consumption. The semiconductor device includes an oxide semiconductor, a first transistor, a second transistor, and a dummy word line. A channel formation region in the first transistor and a channel formation region in the second transistor are formed in different regions in the oxide semiconductor. The dummy word line is provided to extend between the channel formation region in the first transistor and the channel formation region in the second transistor. By applying a predetermined potential to the dummy word line, the first transistor and the second transistor are electrically isolated in a region of the oxide semiconductor which intersects the dummy word line.
    Type: Application
    Filed: January 17, 2017
    Publication date: July 27, 2017
    Inventors: Hiromichi GODO, Tatsunori INOUE
  • Patent number: 9711610
    Abstract: The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 18, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Hiroshi Fujiki, Hiromichi Godo, Yasumasa Yamane
  • Publication number: 20170194466
    Abstract: A semiconductor device in which a shift of the threshold voltage of a transistor is suppressed is provided. A semiconductor device in which a decrease in the on-state current of a transistor is suppressed is provided. The semiconductor device is manufactured as follows: forming a gate electrode layer over a substrate; forming a gate insulating film over the gate electrode layer; forming an oxide semiconductor film over the gate insulating film; forming a metal oxide film having a higher reducing property than the oxide semiconductor film over the oxide semiconductor film; performing heat treatment while the metal oxide film and the oxide semiconductor film are in contact with each other, thereby the metal oxide film is reduced so that a metal film is formed; and processing the metal film to form a source electrode layer and a drain electrode layer.
    Type: Application
    Filed: March 20, 2017
    Publication date: July 6, 2017
    Inventor: Hiromichi GODO
  • Patent number: 9685562
    Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: June 20, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Satoshi Kobayashi
  • Patent number: 9660102
    Abstract: An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.
    Type: Grant
    Filed: April 6, 2015
    Date of Patent: May 23, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Kengo Akimoto, Shunpei Yamazaki
  • Publication number: 20170141351
    Abstract: A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided.
    Type: Application
    Filed: November 23, 2016
    Publication date: May 18, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki SAKAKURA, Hiromichi GODO, Karou TSUCHIYA
  • Patent number: 9601631
    Abstract: A semiconductor device in which a shift of the threshold voltage of a transistor is suppressed is provided. A semiconductor device in which a decrease in the on-state current of a transistor is suppressed is provided. The semiconductor device is manufactured as follows: forming a gate electrode layer over a substrate; forming a gate insulating film over the gate electrode layer; forming an oxide semiconductor film over the gate insulating film; forming a metal oxide film having a higher reducing property than the oxide semiconductor film over the oxide semiconductor film; performing heat treatment while the metal oxide film and the oxide semiconductor film are in contact with each other, thereby the metal oxide film is reduced so that a metal film is formed; and processing the metal film to form a source electrode layer and a drain electrode layer.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventor: Hiromichi Godo
  • Patent number: 9601633
    Abstract: An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time ?1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 21, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Inoue, Masashi Tsubuku, Suzunosuke Hiraishi, Junichiro Sakata, Erumu Kikuchi, Hiromichi Godo, Akiharu Miyanaga, Shunpei Yamazaki